Infineon Technologies TC1784, Руководство пользователя

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TC1784
LMB External Bus Unit
User´s Manual 12-9 V1.1, 2011-05
EBUT13L-A, V1.16
12.5 Start-Up/Boot Process
After reset, the EBU will be configured with access to the external bus disabled(i.e. no
access from LMB to external memory is possible without EBU re-configuration). Only the
register space will be accessible.
12.6 Clocking Strategy and Local Clock Generation
The memory controller is designed to have a flexible internal clocking strategy to allow
the power dissipation of the core to be minimised
12.6.1 Local Clock Divider
A local divider can be used to reduce the frequency of the clock signal used to drive the
core logic of the memory controller (EBU_CLK). The divider can be programmed for
divide ratios of 1:1, 2:1, 3:1 or 4:1 using the EBUCLK.EBUDIV field.
The purposes of the divider is to allow the memory controller core to operate
synchronously at an integer divide ratio of the LMB clock.
As the local clock division circuit uses pulse swallowing to generate the internal clock,
the duty cycle of the internal clock will be distorted when a ratio other than 1:1 is selected.
This will affect the timing of signals generated using the negative edge of the internal
clock and they will be delayed by half an LMB_CLK period from the rising edge and not
half an internal clock period.
Clock ratios can be switched dynamically while the memory controller continues to
process accesses to external memory (provided that the register settings for the memory
are valid for both clock frequencies). To achieve this, the memory controller will wait for
running accesses to complete and then retry incoming accesses until the new clock ratio
is selected and stable. Once the new ratio is selected, the EBU_CLC.divack field will be
updated to show the new ratio.
12.6.2 Standby Mode
The standby mode is enabled by writing 1
B
to the EBU_CLC.DISR field.
Once the bit is set, the memory controller will wait for any running accesses to finish and
will then disable the clock to the core logic.
Exit from standby mode is triggered by writing 0
B
to the EBU_CLC.DISR field
Alternatively, once in standby mode, any valid access to external memory or memory
controller registers arriving on the LMB interface will trigger an automatic exit from
standby mode to service the access request. This condition may also prevent standby
mode being entered at all depending upon when the new access arrives at the interface