Infineon Technologies TC1784, Руководство пользователя

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TC1784
System Control Unit (SCU)
User´s Manual 3-15 V1.1, 2011-05
32-bit SCU, V1.18
The PLL has a lock detection that supervises the VCO part of the PLL in order to
differentiate between stable and instable VCO circuit behavior. The lock detector marks
the VCO circuit and therefore the output
f
VCO
of the VCO as instable if the two inputs
f
REF
and
f
DIV
differ too much. Changes in one or both input frequencies below a level are not
marked by a loss of lock because the VCO can handle such small changes without any
problem for the system.
PLL VCO Loss-of-Lock Event
The PLL may become unlocked, caused by a break of the crystal or the external clock
line. In such a case, an NMI trap is generated if the according NMI trap is enabled.
Additionally, the OSC clock input
f
OSC
is disconnected from the PLL VCO to avoid
unstable operation due to noise or sporadic clock pulses coming from the oscillator
circuit. Without a clock input
f
OSC
, the PLL gradually slows down to its VCO base
frequency and remains there. This automatic feature can be disabled by setting bit
PLLCON0.OSCDISCDIS. If this bit is set the OSC clock remains connected to the VCO.
VCO Power Down Mode
The PLL offers a VCO Power Down Mode. This mode can be entered to save power
within the PLL. The VCO Power Down Mode is entered by setting bit
PLLCON0.VCOPWD. While the PLL is in VCO Power Down Mode only the Prescaler
Mode is operable. Please note that selecting the VCO Power Down Mode does not
automatically switch to the Prescaler Mode. So before the VCO Power Down Mode is
entered the Prescaler Mode must be active.
PLL Power Down Mode
The PLL offers a Power Down Mode. This mode can be entered to save power if the PLL
is not needed at all. The Power Down Mode is entered by setting bit
PLLCON0.PLLPWD. While the PLL is in Power Down Mode no PLL output frequency is
generated.
3.1.1.4 ERAY Phase-Locked Loop (PLL_ERAY) Module
The PLL_ERAY can convert a low-frequency external clock signal to a high-speed
internal clock for maximum performance. The PLL_ERAY also has fail-safe logic that
detects degenerate external clock behavior such as abnormal frequency deviations or a
total loss of the external clock. It can execute emergency actions if it loses its lock on the
external clock.
This module is a phase locked loop for integer frequency synthesis. It allows the use of
input and output frequencies of a wide range by varying the different divider factors.
Features