Infineon Technologies TC1784, Руководство пользователя

Страница: 410 / 2350

TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-42 V1.1, 2011-05
Buses, V1.9
Field Bits Type Description
ERRCNT [15:0] rwh FPI Bus Error Counter
ERRCNT is incremented on every occurrence of an
FPI Bus error. ERRCNT is reset to 0000
H
after the
SBCU_ECON register is read.
1)
TOUT 16 rwh State of FPI Bus Time-Out Signal
This bit indicates the state of the time-out signal at an
FBI Bus error.
0
B
No time-out occurred
1
B
Time-out has occurred
RDY 17 rwh State of FPI Bus Ready Signal
This bit indicates the state of the ready signal at an
FBI Bus error.
0
B
Wait state(s) have been inserted. Ready signal
was active
1
B
Ready signal was inactive
ABT 18 rwh State of FPI Bus Abort Signal
This bit indicates the state of the abort signal at an
FBI Bus error.
0
B
Master has aborted an FPI Bus transfer. Abort
signal was active
1
B
Abort signal was inactive
ACK [20:19] rwh State of FPI Bus Acknowledge Signals
This bit field indicates the acknowledge code that has
been output by the selected slave at an FPI Bus
error. Coding see
Table 4-10 .
SVM 21 rwh State of FPI Bus Supervisor Mode Signal
This bit indicates whether the FPI Bus error occurred
in Supervisor Mode or in User Mode.
0
B
Transfer was initiated in User Mode
1
B
Transfer was initiated in Supervisor Mode
WRN 22 rwh State of FPI Bus Write Signal
This bit indicates whether the FPI Bus error occurred
at a write cycle (see
Table 4-14 ).
RDN 23 rwh State of FPI Bus Read Signal
This bit indicates whether the FPI Bus error occurred
at a read cycle (see
Table 4-14 ).