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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual
21-201
V1.1, 2011-05
GPTA
®
v5, V1.14
ILM
8
rw
Shadow Register Copy Input Line Mode
0
B
LTC63IN is operating in Edge Sensitive Mode.
1
B
LTC63IN is operating in Level Sensitive Mode.
CEN
10
rh
Enable for Shadow Register Copy
0
B
Shadow register copy is currently disabled.
1
B
Shadow register copy is currently enabled.
OUT
15
rh
Output State
0
B
LTC63OUT output line is 0.
1
B
LTC63OUT output line is 1.
0
[7:6], 9,
[14:11],
[31:16]
r
Reserved
Read as 0; should be written with 0.
GPTA0_LTCXRk (k = 00-62)
GPTA0 Local Timer Cell X Register k(204
H
+k*8
H
)
Reset Value: 0000 0000
H
31
16 15
0
0
X
r
rwh
Field Bits
Type Description
X
[15:0]
rwh
Local Timer Data Register Value
0
[31:16] r
Reserved
Read as 0; should be written with 0.
Field Bits
Type Description
Содержание TC1784
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