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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual
21-13
V1.1, 2011-05
GPTA
®
v5, V1.14
FPC Operating Modes
Each filter and prescaler cell can be individually configured to operate in one of the
following operating modes:
•
Delayed Debounce Filter Mode on both edges
•
Immediate Debounce Filter Mode on both edges
•
Rising edge: Immediate Debounce Filter Mode, falling edge: No filtering
•
Rising edge: No filtering, falling edge: Immediate Debounce Filter Mode
•
Rising edge: Delayed Debounce Filter Mode, falling edge: Immediate Debounce
Filter Mode
•
Rising edge: Immediate Debounce Filter Mode, falling edge: Delayed Debounce
Filter Mode
•
Prescaler Mode (triggered by edge detection circuitry on rising edge)
•
Prescaler Mode (triggered by edge detection circuitry on falling edge)
The operation mode is selected by bit field FPCCTRk.MOD (
FPC Input Signals
Bit field FPCCTRk.IPS (see
) selects one of the following inputs for FPCk:
•
Signal input 0 (SINk0)
•
Signal input 1(SINk1)
•
Signal input 2 (SINk2)
•
Signal input 3 (SINk3)
•
GPTA
®
v5 module clock
f
GPTA
(SINk4)
•
Preceding FPC level output signal SOLk-1 (SIN05 is connected to SOL5)
When the preceding FPC level output signal is selected as input, two or more FPCs may
be concatenated; for example, to combine a delayed debounce filter and an immediate
debounce filter.
The maximum FPC input signal frequency must be less than or equal to the sampling
rate (
f
GPTA
/2). The assignment of GPTA
®
v5 I/O line and FPC signal inputs SINk is
defined in
“FPC Input Line Selection” on Page 21-102
FPC Filter Clocks
Bit field FPCCTRk.CLK (see
) selects one of four filter clocks for FPCk:
•
Clock input line 0 (CINk0) = GPTA
®
v5 module clock
f
GPTA
•
Clock input line 1 (CINk1) = local PLL clock,
•
Clock input line 2 (CINk2) = (prescaled) GPTA
®
v5 module clock
f
GPTA
or PLL clock
from other unit or DCM 3 clock
•
Clock input line 3 (CINk3) = DCM 2 clock or PLL clock of other unit or
uncompensated PLL clock or uncompensated PLL clock of other unit
When using a PLL clock for the FPC, no software is needed to adapt the FPC filter to
changing speed for angle-based input signals. The standard PLL clock can be either the
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