Infineon Technologies TC1784, Руководство пользователя

Страница: 1129 / 2350

TC1784
Synchronous Serial Interface (SSC)
User´s Manual 17-8 V1.1, 2011-05
SSC, V1.5
• Only one slave drives the line and enables the driver of its MRST pin. All the other
slaves must program their MRST pins to input. Therefore, only one slave can put its
data onto the master’s receive line. Only reception of data from the master is
possible. The master selects the slave device from which it expects data either by
separate select lines, or by sending a special command to this slave. The selected
slave then switches its MRST line to output until it gets a de-selection signal or
command.
• The slaves use open drain output on MRST. This forms a wired-AND connection.
The receive line needs an external pull-up in this case. Corruption of the data on the
receive line sent by the selected slave is avoided when all slaves not selected for
transmission to the master send only 1s. Since this high level is not actively driven
onto the line, but is only held through the pull-up device, the selected slave can pull
this line actively to a low level when transmitting a zero bit. The master selects the
slave device from which it expects data either by separate select lines, or by sending
a special command to this slave.
After performing all necessary initializations of the SSC, the serial interfaces can be
enabled. For a master device, the alternate clock line will now go to its programmed
polarity. The alternate data line will go to either 0 or 1, until the first transfer starts. After
a transfer, the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register TB. This value is copied into the shift
register (assumed to be empty at this time), and the selected first bit of the transmit data
will be placed onto the MTSR line on the next clock from the shift clock generator
(transmission only starts, if CON.EN = 1). Depending on the selected clock phase, a
clock pulse is generated on the SCLK line. With the opposite clock edge, the master
simultaneously latches and shifts in the data detected at its input line MRST. This
“exchanges” the transmit data with the receive data. Because the clock line is connected
to all slaves, their shift registers will be shifted synchronously with the master’s shift
register, shifting out the data contained in the registers, and shifting in the data detected
at the input line. After the pre-programmed number of clock pulses (via the data width
selection), the data transmitted by the master is contained in all slaves’ shift registers,
while the master’s shift register holds the data of the selected slave. In the master and
all slaves, the content of the shift register is copied into the Receive Buffer (RB) and the
receive interrupt line (RIR) is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at pin MRST when the contents of the transmit buffer are copied into the slave’s
shift register. Bit STAT.BSY is not set until the first clock edge at SCLK appears. The
slave device will not wait for the next clock from the shift clock generator – as the master
does – because the first clock edge generated by the master may be already used to
clock in the first data bit, depending on the selected clock phase. So the slave’s first data
bit must already be valid at this time.