Infineon Technologies TC1784, Руководство пользователя

Страница: 102 / 2350

TC1784
CPU Subsystem
User´s Manual 2-12 V1.1, 2011-05
CPU, V3.03
For instruction fetch requests from the TriCore CPU to ICACHE, the program tag ECC
bits are read along with the data bits and an error flag is computed. A way hit is triggered
only if the tag address comparison succeeds, the valid bit is set and no ECC error in the
associated tag way is detected, any other result is considered a miss. In the normal case
where no error is detected in either cache way then the cache line is filled/refilled as
normal. In the case where an error is detected the cache controller replacement
algorithm forces the way indicating an error to be replaced. Since such errors are
otherwise transparent to the TriCore CPU, the CCPIE_R counter is incremented to allow
counting of such error corrections if required. In the case where one cache way flags a
cache hit, and the other cache way detects an uncorrectable ECC error, the error
condition is masked and has no effect on the memory integrity error handling
mechanisms.
2.3.5.2 Data Side Memories
The data side memories of the TriCore 1.3.1 core support a programmable split between
Local Data RAM (LDRAM) and Data Cache (DCache). Both LDRAM and DCache are
unified within a single memory structure, known as Data Memory (DMEM). The DMEM
of TriCore 1.3.1 is protected from memory integrity errors on a per-halfword basis. Any
byte write access to either LDRAM or DCache is converted to a halfword Read-Modify-
Write sequence. The transformation of such byte accesses to atomic sequences is
performed within the DMI rather than the CPU core itself. In normal operation isolated
byte write transactions to the data memories result in no additional stall cycles.
Local Data RAM (LDRAM)
The Local Data RAM of TriCore 1.3.1 is protected from memory integrity errors on a per-
halfword basis. The LDRAM is ECC protected, six ECC bits are required per half-word
stored. ECC protection of LDRAM is enabled by setting MIECON.DMIEE to one. When
MIECON.DMIEE is zero all uncorrectable memory integrity errors are ignored.
For data load requests from the TriCore CPU to LDRAM, the ECC bits are read along
with the data bits and an uncorrectable error signal is generated for each half-word. If an
error is detected associated with any of the data half-words passed to the core an error
is flagged to the core. If such an error condition is detected an asynchronous DIE trap is
raised. The trap handler is then responsible for correcting the memory entry, or for taking
alternative action (such as system soft reset) if correction of the data is not possible.
For LDRAM read operations from the LMB interface, either from the PMI module or
another LMB master agent, an access that results in the detection of an uncorrectable
error in the requested data half-words causes a bus error to be returned for the bus
transaction. Since the TriCore CPU may not be involved in the transaction, a separate
error is also flagged to the SCU module to optionally generate an NMI trap back to the
core.