Infineon Technologies TC1784, Руководство пользователя

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TC1784
Program Memory Unit (PMU)
User´s Manual 5-6 V1.1, 2011-05
PMU, V1.47
POLDAEN 1 w Protection Bit for OLDAEN
0
B
Bit protection: Bit OLDAEN remains unchanged
with register OVRCON write
1
B
OLDAEN can be changed with current write
access to register OVRCON
This bit enables OLDAEN write during OVRCON write.
Return 0 if read.
PECCCTR 8 w Protection Bit for ECC Control Bits
0
B
Bit protection: The writable ECC control bits
(ECCGENDIS, DBERINTDIS) remain
unchanged with register OVRCON write.
1
B
The ECC control bits can be changed with
current write access to register OVRCON.
Return 0 if read.
ECCGENDIS 9 rw ECC Generation Disable
0
B
Write accesses to the OVRAM use an ECC
calculated from the data.
1
B
Write accesses to the OVRAM use the content
of OVRCON.ECCW instead of generating an
ECC from the data.
DBERINTDIS 13 rw ECC Double-Bit Error Interrupt Disable
0
B
Double-bit errors are reported to the SCU for
NMI triggering and to the redundancy wrapper.
1
B
Double-bit errors are not reported to the SCU
and to the redundancy wrapper.
ECCDBER 15 rwh ECC Double-Bit Error Sticky Flag
This bit is set when a read or read-modify-write access
had a double-bit error.
It can be cleared by writing a 0.
ECCW [23:16] rw ECC Write Data
When the ECC encoding of the OVRAM is disabled
with OVRCON.ECCGENDIS=1 the write accesses
write this data field into the SRAM instead of the
generated ECC code.
0 [31:24],
14, 13,
12, 10,
11, [7:2] r Reserved
Reserved for future use. Write 0, read 0.
Field Bits Type Description