Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-272 V1.1, 2011-05
GPTA
®
v5, V1.14
their input lines IN[31:0] and output lines OUT[31:0] are assigned to six 8-bit port groups
two 7-bit port groups, one 6-bit port group, two 4-bit port groups, one 3-bit port group,
and one 1-bit port group.
Figure 21-95 I/O Port Line Assignment
The interconnections between the GPTA0 unit and the port I/O lines are controlled in the
port logics. The following port control operations selections must be executed:
•
Input/output function selection (IOCR registers)
Mca05997_TC 1784.vsd
8
IOG0
OG0
IOG0
IOG0
IOG0
Port Control
[7:0]
[63:56]
[7:0]
IOG1
OG1
IOG1
IOG1
IOG1
[15:8]
[65:64]
[15:8]
[15:8]
IOG2
OG2
IOG2
IOG2
IOG2
[23:16]
[79:72]
[23:16]
[23:16]
IOG4
OG6
IOG3
IOG4
[39:32]
[111:110]
[31:28]
[39:32]
IN[31:0](to LTCA2)
P0.[7:0]
P0.[15:8]
P1.[7:0]
P2.[7:0]
8
8
7
8
OUT[55:0] (from GPTA0)
OUT[111:56] (from GPTA0)
OUT[31:0] (from LTCA 2)
OUT[111 :80] (from LTCA 2)
IN[55:0](to GPTA0)
[7:0]
[7:0]
[9:8]
[23:19]
4
P4.[3:0]
IOG3
IOG6
IOG2
IOG3
IOG6
IOG2
P1.[14:8]
[31:24]
[55:48]
[18:16]
[31:24]
[55:48]
IOG0
IOG1
[3:0]
[13:10]
P2.[13:8]
6
IOG5
IOG1
IOG5
IOG3
[47:40]
[15:8]
[47:40]
P5.[7:0]
8
[31:26]
OG4 [95:89] P5.[15:8]
8
P6.[3:0]
4
OG3
IOG0
IOG2
IOG3
[83:80]
[7:4]
[15:14]
[25:24]
[18:16]
OG3
OG4
[87:84]
[89:88]
P3.[7:0]
8
OG4
OG5
[95:90]
[97:96]
P3.[15:8]
8