Infineon Technologies TC1784, Руководство пользователя

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TC1784
System Control Unit (SCU)
User´s Manual 3-7 V1.1, 2011-05
32-bit SCU, V1.18
3.1.1.3 Phase-Locked Loop (PLL) Module
The PLL can convert a low-frequency external clock signal to a high-speed internal clock
for maximum performance. The PLL also has fail-safe logic that detects degenerate
external clock behavior such as abnormal frequency deviations or a total loss of the
external clock. It can execute emergency actions if it loses its lock on the external clock.
This module is a phase locked loop for integer frequency synthesis. It allows the use of
input and output frequencies of a wide range by varying the different divider factors.
Features
• VCO lock detection
• 4-bit input divider P: (divide by PDIV+1)
• 7-bit feedback divider N : (multiply by NDIV+1)
• 7-bit output divider K1 or K2: (divide by either by K1DIV+1 or K2DIV+1)
• Oscillator Watchdog
– Detecting too low input frequencies
– Detecting too high input frequencies
– Spike detection for the OSC input frequency
• Different operating modes
– Prescaler Mode
– Freerunning Mode
– Normal Mode
• VCO Power Down
• Glitchless switching between both K-Dividers
• Glitchless switching between Normal Mode and Prescaler Mode
PLL Functional Description
The PLL consists of a Voltage Controlled Oscillator (VCO) with a feedback path. A
divider in the feedback path (N-Divider) divides the VCO frequency down. The resulting
frequency is then compared with the externally provided and divided frequency (P-
Divider). The phase detection logic determines the difference between the two clocks
and accordingly controls the frequency of the VCO (
f
VCO
). A PLL lock detection unit
monitors and signals this condition. The phase detection logic continues to monitor the
two clocks and adjusts the VCO clock if required. The PLL output clock
f
PLL
is derived
from the VCO clock by the K2-Divider or from the oscillator clock and the K1-Divider.
The following figure shows the PLL block structure.