Infineon Technologies TC1784, Руководство пользователя

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TC1784
LMB External Bus Unit
User´s Manual 12-37 V1.1, 2011-05
EBUT13L-A, V1.16
The R/B input from the NAND flash is connected to the memory controller WAIT input
and is available as the EBU_MODCON.STS. This enables a NAND flash to be driven by
software from the processor.
As shown above only two address lines are connected to the Nand Flash, and rather
than being connected to address inputs, they are connected to control inputs. This allows
access to three “registers” in the Nand Flash as follows:-
Note: LMB addresses are byte addresses and addresses on the external bus are 16 bit
word addresses. Therefore [LMB address(18)]->[external address(17)] and [LMB
address(17)]->[external address(16)].
Note that the Memory Controller does not directly support byte wide devices. Writes to
8 bit, NAND Flash devices must therefore be done as 16-bit word writes with the valid
byte in the lower part and the upper-byte padded.
12.10.6.1 NAND flash page mode
NAND flash memories are page oriented devices capable of extended read operations
with a single setup phase for command signals at the beginning of the access. The
asynchronous controller of the Memory Controller will split a large transfer into multiple
accesses to external memory but each of these accesses will have the overhead of the
initial setup phase. Enabling page mode, using the agen field in EBU_BUSCONx will
cause the standard flow of the controller to be modified as follows:
•
For a read, if data remains to be fetched at the end of a command phase, the
controller will start a new command delay phase, instead of a new address phase or
recovery phase and the address will not be incremented. If
EBU_BUSRAPx.cmddelay is set to zero, the command delay phase will have a
duration of one clock cycle but in this case the command delay phase is mandatory
to ensure that the RD and RD/WR signals return to the high state.
• For a write, if data remains to be written at the end of a data hold phase (or command
phase if the length of data hold is zero), the controller will start a new command
phase, instead of a new address phase or recovery phase and the address will not
be incremented. If EBU_BUSWAPx.datac is set to zero, the data hold phase will have
Table 12-21 Nand Flash “Registers”
LMB Address
“Register” Comment
Base + 00000
H
Data Register Read/Write: Used to read data from and write
data to the device.
Base + 20000
H
Address Register Write only: Used to write the required access
address to the device.
Base + 40000
H
Command Register Write only: Used to write the required
command to the device.