Infineon Technologies TC1784, Руководство пользователя

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-24 V1.1, 2011-05
DMA, V3.03
CHCRmn.DMAPRIO value determines the priority on the DMA Bus Switch (see
Table 11-2 ).
11.2.7 DMA Module Priorities on On Chip Busses (
FPI Bus, LMB Bus)
Every active peripheral connected to the DMA Bus Switch that requests for access to FPI
Bus or LMB Bus has to go through two arbitration stages before accessing the On Chip
Bus: DMA Module internal arbitration at the DMA Bus Switch and DMA Module external
arbitration at the On Chip Bus.
Table 11-1 DMA Bus Switch Priorities
Priority Agent Requests Comment
Highest Cerberus to On Chip Bus High Priority selection by software in Cerberus.
FPI Bus to DMA Peripheral
Interface accesses
Reason: minimizing wait states on the
FPI Bus.
DMA Move Engine Write The detailed Bus Switch priorities for the
two Engines with concurrent reads or
concurrent writes are listed in
Table 11-2 .
DMA Move Engine Read The detailed Bus Switch priorities for the
two Engines with concurrent reads or
concurrent writes are listed in
Table 11-2 .
MLI0 access –
Lowest Cerberus to On Chip Bus Low Priority selection by software in Cerberus.
Table 11-2 DMA Bus Switch Priorities of DMA Move Engines
Priority DMA Move Engine Request Comment
Highest
Lowest
Move Engine 0
CHCR0x.DMAPRIO = “11” or
CHCR0x.DMAPRIO = “01” (x=7-0).
x reflects the channel of Move 0 that won
the Move Engine internal arbitration.
Move Engine 1
CHCR1y.DMAPRIO = “11” or
CHCR1y.DMAPRIO = “01” (y=7-0).
y reflects the channel of Move 1 that won
the Move Engine internal arbitration.
Move Engine 0
CHCR0x.DMAPRIO = “00” (x=7-0).
x reflects the channel of Move 0 that won
the Move Engine internal arbitration.
Move Engine 1
CHCR1x.DMAPRIO = “00” (y=7-0).
y reflects the channel of Move 1 that won
the Move Engine internal arbitration.