Infineon Technologies TC1784, Руководство пользователя

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TC1784
Memory Maps
User´s Manual 8-1 V1.1, 2011-05
MemMaps, V1.91
8 Memory Maps
This chapter gives an overview of the TC1784 memory map, and describes the address
locations and access possibilities for the units, memories, and reserved areas as “seen”
from the two different on-chip buses’ point of view.
The TC1784 has the following memories
•
Program Memory Unit (PMU) with
– 2,5 Mbyte of Program Flash Memory (PFLASH)
– 128 Kbyte of Data Flash Memory (DFLASH)
– 16 Kbyte of Boot ROM (BROM)
– 8 KB Overlay Memory (OVRAM
1)
)
• Program Memory Interface (PMI)
– 40 Kbyte of Scratch-Pad RAM (SPRAM
2)1)
)
– 16 Kbyte of Instruction Cache (ICACHE
2)1)
)
• Data Memory Interface (DMI)
– 128 Kbyte of Local Data RAM (LDRAM
3)1)
)
– 4 Kbyte of Data Cache (DCACHE
3)
)
• PCP memory
– 32 Kbyte of PCP Code Memory (CMEM
1)
)
– 16 Kbyte of PCP Data Memory (PRAM
1)
)
Furthermore, the TC1784 has two on-chip buses:
•
System Peripheral Bus (SPB)
• Local Memory Bus (LMB)
1) Before enabeling error detection, the memory has to be initialized by customer SW
2) Up to 16 Kbyte out of the 40 Kbyte SPRAM can be configured as ICache. The supported SPRAM / ICache
configurations are described in the CPU sub-chapter: ´Program Memory Interface (PMI)‘.
3) Up to 4 Kbyte out of the 128 Kbyte LDRAM can be configured as DCache. The supported LDRAM / DCache
configurations are described in the CPU sub-chapter: ´Data Memory Interface (DMI)‘.