Infineon Technologies TC1784, Руководство пользователя

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TC1784
Direct Memory Access Controller (DMA)
User´s Manual 11-52 V1.1, 2011-05
DMA, V3.03
- Reserved 280
H
-
29C
H
BE BE - -
DMA_
MLI0SRC3 DMA MLI0 Service
Request Control Reg.
3 2A0
H
U, SV SV 3 Page 11-124
DMA_
MLI0SRC2 DMA MLI0 Service
Request Control Reg.
2 2A4
H
U, SV SV 3 Page 11-124
DMA_
MLI0SRC1 DMA MLI0 Service
Request Control Reg.
1 2A8
H
U, SV SV 3 Page 11-124
DMA_
MLI0SRC0 DMA MLI0 Service
Request Control Reg.
0 2AC
H
U, SV SV 3 Page 11-124
– Reserved 2B0
H
-
2DC
H
BE BE - -
DMA_
SRC7 DMA Service Request
Control Register 7 2E0
H
U, SV SV 3 Page 11-123
DMA_
SRC6 DMA Service Request
Control Register 6 2E4
H
U, SV SV 3 Page 11-123
DMA_
SRC5 DMA Service Request
Control Register 5 2E8
H
U, SV SV 3 Page 11-123
DMA_
SRC4 DMA Service Request
Control Register 4 2EC
H
U, SV SV 3 Page 11-123
DMA_
SRC3 DMA Service Request
Control Register 3 2F0
H
U, SV SV 3 Page 11-123
DMA_
SRC2 DMA Service Request
Control Register 2 2F4
H
U, SV SV 3 Page 11-123
DMA_
SRC1 DMA Service Request
Control Register 1 2F8
H
U, SV SV 3 Page 11-123
DMA_
SRC0 DMA Service Request
Control Register 0 2FC
H
U, SV SV 3 Page 11-123
1) The absolute register address is calculated as follows:
Module Base Address ( Table 11-7 ) + Offset Address (shown in this column)
Further, the following ranges for parameters i, k, x, and n are valid: i = 0-7, k = 0-7, x = 0-1, n = 0-63.
Table 11-8 Registers Overview - DMA Control Registers
Short
Name Description Offset
Addr.
1)
Access Mode Reset
Class
Description
See
Read Write