Infineon Technologies TC1784, Руководство пользователя

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TC1784
General Purpose I/O Ports and Peripheral I/O Lines (Ports)
User´s Manual 9-41 V1.1, 2011-05
Ports, V1.1
9.5.3 Port 2 Registers
The following registers are available on Port 2:
9.5.3.1 Port 2 Output Register
The basic P2_OUT register functionality is described on Page 9-16 . Port lines P2.[15:14]
are not connected to port lines. Therefore, reading the P2_OUT bits P[15:14] returns the
value that was last written (0 after reset). These bits can also be set/reset by the
corresponding P2_OMR bits.
9.5.3.2 Port 2 Output Modification Register
The basic P2_OMR register functionality is described on Page 9-17 . However, port lines
P2.15 and P2.14 are not available. Therefore, the P2_OMR bits PS[15:14] and
PR[15:14] have no direct effect on port lines but only on register bits P2_OUT.P[15:14].
9.5.3.3 Port 2 Input Register
The basic P2_IN register functionality is described on Page 9-20 . However, port lines
P2.14 and P2.15 are not available. Therefore, bits P14 and P15 in register P2_IN are
always read as 0.
Table 9-15 Port 2 Registers
Register
Short Name Register Long Name Offset
Address Description
see
P2_OUT Port 2 Output Register 00
H
below
1)
1) These registers are listed and noted here in the Port 2 section because they differ from the general port
register description given in Section 9.2 .
P2_OMR Port 2 Output Modification Register 04
H
P2_IOCR0 Port 2 Input/Output Control Register 0 10
H
Page 9-8
P2_IOCR4 Port 2 Input/Output Control Register 4 14
H
Page 9-9
P2_IOCR8 Port 2 Input/Output Control Register 8 18
H
Page 9-9
P2_IOCR12 Port 2 Input/Output Control Register 12 1C
H
Page 9-9
P2_IN Port 2 Input Register 24
H
Page 9-41
1)
P2_PDR Port 2 Pad Driver Mode Register 40
H
Page 9-42
1)
P2_ESR Port 2 Emergency Stop Register 50
H
Page 9-42
1)