Infineon Technologies TC1784, Руководство пользователя

Страница: 421 / 2350

TC1784
On-Chip System Buses and Bus Bridges
User´s Manual 4-53 V1.1, 2011-05
Buses, V1.9
DMAM 4 rh High-Priority DMA FPI Bus Master Status
2)
This bit indicates whether the DMA with a medium
priority request was FPI Bus master when the break
trigger event occurred.
0
B
The medium-priority DMA was not the FPI bus
master.
1
B
The medium-priority DMA was the FPI Bus
master.
LFI 5 rh LFI Bridge FPI Bus Master Status
This bit indicates whether the LFI Bridge was
FPI Bus master when the break trigger event
occurred.
0
B
The LFI Bridge was not an FPI Bus master.
1
B
The LFI Bridge was FPI Bus master.
DMAL 6 rh Low-Priority DMA FPI Bus Master Status
3)
This bit indicates whether the DMA with a low-
priority request was the FPI Bus master when the
break trigger event occurred.
0
B
The low-priority DMA was not the FPI Bus
master.
1
B
The low-priority DMA was the FPI Bus master.
CHNR0y
(y = 0-7) 16+y rh DMA Channel Number Status
These bits indicate which DMA channel with number
0y was active when a DMA break trigger event
occurred.
0
B
DMA channel 0y was not active at a DMA
break trigger event.
1
B
DMA channel 0y was active at a DMA break
trigger event.
ONE,
ONE [15:7],
[2:1] r Reserved
Read as 1; should be written with 0.
0 [31:24] r Reserved
Read as 0; should be written with 0.
1) Including DMA transactions from DMA channels with high priority and from Cerberus with high priority.
2) Including DMA transactions from DMA channels with medium priority.
3) Including DMA transactions from DMA channels with low priority, MLI and from Cerberus with low priority.
Field Bits Type Description