Infineon Technologies TC1784, Руководство пользователя

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TC1784
LMB External Bus Unit
User´s Manual 12-60 V1.1, 2011-05
EBUT13L-A, V1.16
WAITRDC 11:7 rw Programmed Wait States for read accesses
Number of programmed wait states for read
accesses. For synchronous accesses, this will always
be adjusted so that the phase exits on a rising edge
of the external clock.
00000
B
1 wait state.
00001
B
1 wait states.
00010
B
2 wait state.
…
B
…
11110
B
30 wait states.
11111
B
31 wait states.
DATAC 15:12 rw Data Hold Cycles for Read Accesses
This bit field determines the basic number of Data
Hold phase clock cycles during read accesses. It has
no effect in the current implementation
xxxx
B
No data hold clock cycles available.
EXTCLOCK 17:16 rw Frequency of external clock at pin BFCLKO
BFCLKO is not implemented but this field can effect
the relative timing of some output signals. See
“Control of ADV & Other Signal Delays During
Asynchronous Accesses” on Page 12-32
.
EXTDATA 19:18 rw Extended data
Reserved, write 11
B
.
CMDDELAY 23:20 rw Command Delay Cycles
This bit field determines the basic number of
Command Delay phase clock cycles.
0000
B
0 clock cycle selected.
0001
B
1 clock cycle selected.
…
B
…
1110
B
14 clock cycles selected.
1111
B
15 clock cycles selected.
AHOLDC 27:24 rw Address Hold Cycles
This bit field determines the number of clock cycles of
the address hold phase..
0000
B
0 clock cycles selected
0001
B
1 clock cycle selected
…
B
…
1110
B
14 clock cycles selected
1111
B
15 clock cycles selected
Field Bits Type Description