Infineon Technologies TC1784, Руководство пользователя

Страница: 1936 / 2350

TC1784
General Purpose Timer Array (GPTA
®
v5)
User´s Manual 21-284 V1.1, 2011-05
GPTA
®
v5, V1.14
System Control Unit
The SCU contains the external request unit (ERU), which is especially responsible for
controlling requests coming from the MSC modules, port pins, or from the
GPTA0/LTCA2 unit and passing these request to AD converters, DMA controller, or
interrupt nodes.
MultiCAN Connections
The MultiCAN controller has the following connections to the GPTA0/LTCA2 unit:
•
MultiCAN service request output SR15 is connected to the INT0 input of
GPTA0/LTCA2.
DMA Controller
As shown in Figure 21-98 , eight GPTA0 on-chip trigger and gating output lines are
connected as trigger input signals to the DMA request inputs. Furthermore the external
request unit generates four DMA request output signals (IOUT[3:0]) that can be activated
via port pins, the MSC clock outputs, or the four GPTA
®
v5 output lines. Three of these
four DMA request output signals are connected to the GPTA0/LTCA2 internal inputs
INT[3:1]. These connections allow, for example, GTC or LTC events in the GPTA
®
v5
units to be triggered by a request coming from a port pin or from the MSC clock.
ADC Connections
As shown in Figure 21-98 , for each ADC nine GPTA0 on-chip trigger and gating output
lines are connected as trigger input signals or gating input signals to the channel trigger
logic of the ADC. Thus dedicated GPTA0 outputs can generate trigger events or act as
gating signals for ADC channels. Furthermore the external request unit generates two
ADC conversion trigger signals (IOUT[3:2]) and two ADC conversion gating signals
(PDOUT[3:2]) that can be activated each via port pins, the MSC clock outputs, or two
GPTA
®
v5 output lines.
FADC Connections
As shown in Figure 21-98 , eight GPTA0 on-chip trigger and gating output lines are
connected as trigger input signals or gating input signals to the channel trigger logic of
the FADC. Thus dedicated GPTA0 outputs can generate trigger events or act as gating
signals for FADC channels.
Port Connections of Input IN0
The common input line IN0 of the GPTA0/LTCA2 unit is connected to the output of a 2-
to-1 multiplexer. This multiplexer is controlled by bit field SCU_EXTCON.GPTAINSEL
and allows the common GPTA0/LTCA2 input IN0 to be connected to one out of two input
lines. This feature especially allows the number of clock of the PLL (to determine clock