Infineon Technologies TC1784, Руководство пользователя

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TC1784
Peripheral Control Processor (PCP)
User´s Manual 10-57 V1.1, 2011-05
PCP, V2.09
This function is controlled by the RPROT register ( “Register Protection Register,
PCP_RPROT” on Page 80 ).
10.13.2 Access to the PRAM from the FPI Bus
FPI Bus accesses to the PRAM must always be performed with word accesses; byte or
half-word accesses will result in a bus error.
Attention needs to be paid when accessing the CSAs and data sections of the PCP
channel programs. The location of a specific channel’s CSA is dependent on the chosen
Context Model, Full, Small or Minimum Context.
Table 30 shows these addresses.
Note: Since channel 0 is not defined (no service request with SRPN = 0), the first area
is not an actual CSA. It is recommended that this area should not be used by PCP
channel programs.
The FPI Bus address of a word location pointed to by the Data Pointer R7_DPTR is
calculated by the following formula:
•
Effective FPI Bus address[31:0] = (PRAM Base Address) + (<DPTR> << 6)
10.13.3 Access to the CMEM from the FPI Bus
FPI Bus accesses to the CMEM must always be performed with word accesses; byte or
half-word accesses will result in a bus error.
When using a channel entry table, the FPI Bus address of a specific channel’s entry
location is given by the following formula:
•
Effective FPI Bus address[31:0] = (CMEM Base Address) + 04
H
×
channel number
Table 30 FPI Bus Access to CSAs
Channel Full Context Small Context Minimum Context
0 (see
note) PRAM Base A
00
H
PRAM Base A
00
H
PRAM Base A
00
H
1 PRAM Base A
20
H
PRAM Base A
10
H
PRAM Base A
08
H
2 PRAM Base A
40
H
PRAM Base A
20
H
PRAM Base A
10
H
3 PRAM Base A
60
H
PRAM Base A
30
H
PRAM Base A
18
H
n PRAM Base A
n
×
20
H
PRAM Base A
n
×
10
H
PRAM Base A
n
×
08
H