Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
167
Intel XScale
®
Processor—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
As an example, assume the following values in CCNT, PMN0, PMN1 and PMNC:
In the contrived example above, the instruction cache had a miss-rate of 5% and CPI
was 2.4.
3.8
Programming Model
This section describes the programming model of the IXP45X/IXP46X network
processors, namely the implementation options and extensions to the Intel
®
StrongARM
*
Version 5TE architecture.
3.8.1
Intel
®
StrongARM
*
Architecture Compatibility
The IXP45X/IXP46X network processors implement the integer instruction set
architecture specified in Intel
®
StrongARM
*
V5TE. T refers to the thumb instruction set
and E refers to the DSP-Enhanced instruction set.
Intel StrongARM V5TE introduces a few more architecture features over Intel
StrongARM V4, specifically the addition of tiny pages (1 Kbyte), a new instruction that
counts the leading zeroes (CLZ) in a data value, enhanced Intel StrongARM-Thumb
transfer instructions and a modification of the system control coprocessor, CP15.
Example 15. Interrupt Handling
IRQ_INTERRUPT_SERVICE_ROUTINE:
; Assume that performance counting interrupts are the only IRQ in the system
MRC P14,0,R1,C0,c1,0
; read the PMNC register
BIC R2,R1,#1
; clear the enable bit, preserve other bits in PMNC
MCR P14,0,R2,C0,c1,0
; disable counting
MRC P14,0,R3,C1,c1,0
; read CCNT register
MRC P14,0,R4,C0,c2,0
; read PMN0 register
MRC P14,0,R5,C1,c2,0
; read PMN1 register
<process the results>
SUBS PC,R14,#4
; return from interrupt
Example 16. Computing the Results
; Assume CCNT overflowed
CCNT = 0x0000,0020 ;Overflowed and continued counting
Number of instructions executed = PMN0 = 0x6AAA,AAAA
Number of instruction cache miss requests = PMN1 = 0x0555,5555
Instruction Cache miss-rate = 100 * PMN1/PMN0 = 5%
CPI = (CCNT + 2^32)/Number of instructions executed = 2.4 cycles/instruction