Intel IXP45X, Developer'S Manual

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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—PCI Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Develepor’s Manual August 2006
558 Order Number: 306262-004US
10.5.3 PCI Controller Configuration and Status Registers (CSRs)
These registers are accessible from the AHB bus and are memory mapped in the AHB
address space. When the arbs_hsel_ppc_mmr is asserted, the lower AHB address bits
select the accessed register. Registers are byte writable with individual bytes addressed
according to the endianness setting of the AHB bus in pci_csr.ABE. Table 201 shows the
address map for the CSRs. The AHB offset is relative to the base address for PCI
Controller memory mapped registers in the AHB address space. The PCI offset is
relative to the base address in pci_bar4 for accesses from the PCI bus. Byte addressing
from PCI uses the PCI byte enable convention.
Register pci_rtotto
Bits Name Description
Reset
Value
PCI
Access
AHB
Access
31:1
6
reserved Reserved 0x00 RO RO
15:8 RetryTO
Specifies value for the Retry timer. Specifies the maximum number of
retries the Master Interface will accept before terminating the transaction.
A value of 0 disables the timer and allows an unlimited number of Retry
responses.
0x80 RW RW
7:0 TRDYTO
Specifies value for the TRDY timer. Specifies the number of PCI clocks the
Master Interface will wait before terminating a transfer with Master Abort
when a target accepts a transaction by asserting PCI_DEVSEL_N but does
not assert PCI_TRDY_N or PCI_STOP_N. A value of 0 disables the timer
and the Master Interface will wait indefinitely for the Target to respond.
0x80 RW RW
Table 201. CSR Address Map (Sheet 1 of 2)
AHB
Offset
PCI
Offset
Register Name Description Reset Value Page
0x00 0x00 pci_np_ad PCI non-prefetch address register 0x00000000 559
0x04 0x04 pci_np_cbe PCI non-prefetch command/byte enables register 0x00000000 559
0x08 0x08 pci_np_wdata PCI non-prefetch write data register 0x00000000 560
0x0c 0x0c pci_np_rdata PCI non-prefetch read data register 0x00000000 560
0x10 0x10 pci_crp_ad_cbe
PCI configuration port address/cmd/byte enables
register
0x00000000 561
0x14 0x14 pci_crp_wdata PCI configuration port write data register 0x00000000 562
0x18 0x18 pci_crp_rdata PCI configuration port read data register 0x00000000 562
0x1c 0x1c pci_csr PCI Controller Control and Status register 0x0000000x 563
0x20 0x20 pci_isr PCI Controller Interrupt Status register 0x00000000 564
0x24 0x24 pci_inten PCI Controller Interrupt Enable register 0x00000000 565
0x28 0x28 pci_dmactrl DMA control register 0x00000000 565
0x2c 0x2c pci_ahbmembase AHB Memory Base Address Register 0xc0000000 566
0x30 0x30 pci_ahbiobase AHB I/O Base Address Register 0x00000000 567
0x34 0x34 pci_ahbmembase PCI Memory Base Address Register 0x00000000 566
0x38 0x38 pci_ahbdoorbell AHB Doorbell Register 0x00000000 568
0x3c 0x3c pci_pcidoorbell PCI Doorbell Register 0x00000000 569
0x40 0x40 pci_atpdma0_ahbaddr AHB-to-PCI DMA AHB Address Register 0 0x00000000 569
0x44 0x44 pci_atpdma0_pciaddr AHB-to-PCI DMA PCI Address Register 0 0x00000000 570
0x48 0x48 pci_atpdma0_length AHB-to-PCI DMA Length Register 0 0x00000000 570