Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Functional Overview
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
54
Reference Number: 306262-004US
illustrates the supported DDRI SDRAM configurations for the
IXP45X/IXP46X network processors. The 128/256/512-Mbit, 1-Gbit DDRI SDRAM
devices comprise four internal leaves. The MCU controls the leaf selects within 128/
256/512-Mbit, 1-Gbit DDRI SDRAM by toggling DDRI_BA[0] and DDRI_BA[1].
The two DDRI SDRAM chip enables DDRI_CS_N[1:0] support a DDRI SDRAM memory
subsystem consisting of two banks. The base address for the two contiguous banks are
programmed in the DDRI SDRAM Base Register (SDBR) and must be aligned to a 32-
Mbyte boundary. The size of each DDRI SDRAM bank is programmed with the DDRI
SDRAM boundary registers (SBR0 and SBR1).
The memory controller is a 32-bit only interface. If a x16 memory chip is used, a
minimum of two memory chips would be required to facilitate the 32-bit interface
required by the IXP45X/IXP46X network processors. If ECC is required, additional
memories would need to be added. For more information on DDRI SDRAM support and
configuration see the Memory Controller section contained later in this document.
The memory controller internally interfaces to the North AHB, South AHB, and Memory
Port Interface with independent interfaces. This architecture allows DDRI SDRAM
transfers to be interleaved and pipelined to achieve maximum possible efficiency.
2.1.8
Expansion Interface
The expansion interface allows easy and — in most cases — glue-less connection to
peripheral devices. It also provides input information for device configuration after
reset.
Table 3.
Supported DDRI Memory Configurations
DDRI SDRAM
Technology
DDRI SDRAM
Arrangement
# Banks
Address Size
Leaf Select
Total
Memory
Size
1
Row
Col
DDRI_BA[1]
DDRI_BA[0]
128 Mbit
16M x 8
1
12
10
I_AD[26]
I_AD[25]
64 Mbyte
2
128 Mbyte
8M x 16
1
12
9
I_AD[25]
I_AD[24]
32 Mbyte
2
64 Mbyte
256 Mbit
32M x 8
1
13
10
I_AD[27]
I_AD[26]
128 Mbyte
2
256 Mbyte
16M x 16
1
13
9
I_AD[26]
I_AD[25]
64 Mbyte
2
128 Mbyte
512 Mbit
64M x 8
1
13
11
I_AD[28]
I_AD[27]
256 Mbyte
2
512 Mbyte
32M x 16
1
13
10
I_AD[27]
I_AD[26]
128 Mbyte
2
256 Mbyte
1 Gbit
128M x 8
1
14
11
I_AD[29]
I_AD[28]
512 Mbyte
2
1 Gbyte
64M x 16
1
14
10
I_AD[28]
I_AD[27]
256 Mbyte
2
512 Mbyte
Notes:
1.
Table indicates 32-bit-wide memory subsystem sizes
