Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—AHB Queue Manager
(AQM)
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
932
Reference Number: 306262-004US
To access any given queue, after the selected queue configuration is read from SRAM,
the queue base address is summed with the read or write pointer to form the queue
address. If the queue isn’t empty, when the request is a read, or full, when the request
is a write, queue control will perform the requested queue access at the calculated
queue address. If the request is a read, the queue data read from SRAM at the
calculated queue address is passed to the AHB interface for the corresponding data
acknowledge to the AHB read request. If the request is a write, the data from the AHB
interface is written into SRAM at the calculated queue address. When the read and
write pointers are equal, the queue is either full or empty as determined by the full or
empty status flags.
When a read request of an empty queue buffer is performed, queue control will return
zeroes in the data field to the AHB interface and will set the Underflow Status Flag.
When a write request of a full queue is performed, the data is discarded and queue
control will set the Overflow Status Flag. Underflow and Overflow Status Flags are
maintained on queues 0-31 only. Otherwise for a read request of an empty queue or
write request of a full queue, queue control will not perform any action upon the queue
buffer or queue configuration word.
Following the queue access, the appropriate read or write pointer, as indicated by the
type of queue access, is incremented and the queue configuration word, with all other
fields maintained, is written back into SRAM. The queue size will be used in determining
the number of active bits within the allocated 7 bit field for the read and write pointers.
Configurable queue sizes of 16, 32, 64 and 128 directly correspond to read and write
active bit widths of 4, 5, 6, and 7. The unused bits of the read and write pointers will be
zeroed prior to writing the queue configuration word back into SRAM.
One to four Queue Access Register addresses, 0, 4, 8, and 0xC, are allocated per queue
as determined by the queue’s programmed entry size. Thus a queue, with an entry size
set to one word, will support accesses to the first location, 0, and a queue with an entry
size set to two, will support accesses to the first and second locations, 0 and 4. A queue
with an entry size set to four words will support accesses to all four locations. Accesses
to the non-supported locations will not be performed and queue read/write pointers will
be unchanged. A queue, with a programmed entry size of two or four words, requires
the two or four accesses of each queue entry to be performed sequentially beginning
with address 0. Accesses performed out of order will not be performed. Incomplete
accesses (e.g. reading only the first two words of a four word entry) will not update the
pointers. The sequential accesses can be performed via multiple single word accesses
or via a burst access on the AHB. If a Queue burst access of more than four words is
attempted, the AQM will perform the accesses to the first two or four locations, as
determined by the queue’s entry size, and the remainder of the accesses of the burst
will not be performed. Queue read accesses which are not performed, will return zeroes
in the data field on the AHB.
Note that the entry size parameter does not affect the data type. The AQM does not
know the semantic meaning of the entries in the queues, they are all simply 32-bit
words. These entries may be pointers, data blocks, big-endian packed data or little-
endian packed data. The entry size does not really change anything except how the
AHB can optimize a transfer. For example, if an entry size is set to two words, a device
on the AHB can read and write this queue in a bus burst operation of length two, which
will optimize bus access. An entry size of four words enables a bus burst of length 4.
Obviously, to support bursting on AHB, one must have consecutive addresses since that
is how the protocol works, and so to support this the entries have multiple addresses.
Of course individual reads and writes may be performed to these consecutive
addresses, but unless there is some kind of bursting, the difference between individual
reads to the same location and individual reads to consecutive locations is small. This
means that unless a given AHB source device is using a burst access to read or write
the AQM there is little AHB performance benefit to programming the word size of two or
four (although there may be software advantages).
