Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
681
Expansion Bus Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
12.4.1.8.18 TI* HPI-16, Simplex-Mode Write Access
12.4.1.8.19 TI* HPI-16, Simplex-Mode Read Access
12.4.2
Inbound Transfers
Inbound transfers are initiated by external masters and target IXP45X/IXP46X network
processors when EX_SLAVE_CS_N is asserted. The Expansion bus controller should
ignore all control signals when EX_SLAVE_CS_N is not asserted and never drive
EX_WAIT_N/EX_DATA/EX_PARITY when its not being accessed. External masters must
request the Expansion bus and only own the bus when it is granted. Refer to
for more information.
The Expansion bus controller has a 1-deep inbound queue that contains one address
register and 8 data registers. The Expansion bus only supports 32-bit masters which
means no byte lane shifting hardware is needed. Therefore bits 31:0 of EX_DATA bus
always translates to bits 31:0 of the AHB DATA bus when EXP_BYTE_SWAP_EN is
disabled. The Expansion bus controller supports word aligned read transfers for 1-word
Figure 146. Expansion Bus Write (TI* HPI-16, Simplex Mode)
Figure 147. Expansion Bus Read (TI* HPI-16, Simplex Mode)
EX_CLK
EX_CS_N[0]
(hcs_n)
EX_ADDR[24:0]
(ha)
EX_RDY_N
(hrdy)
EX_DATA[31:0]
(hdin)
Valid Data
EX_RD_N
(hr_w_n)
Valid Address
T
recov
T
data_setup
T
add_setup
T1
T2
T3
T4
T5
EX_WR_N
(hds1_n)
T
hds1_pulse
T
cs2hds1val
EX_BE_N[3:0]
Valid Byte
3-4 Cycles
3-4 Cycles
2-16 Cycles
3-4 Cycles
2-17 Cycles
B3758-001
EX_CLK
EX_CS_N[0]
(hcs_n)
EX_ADDR[24:0]
(hcntl)
EX_RDY_N
(hrdy)
EX_DATA[31:0]
(hdout)
Valid Data
EX_RD_N
(hr_w_n)
Valid Address
T
recov
T
data_setup
T
cs2hds1val
T
addsetup
T1
T2
T3
T4
T5
EX_WR_N
(hds1_n)
T
hds1_pulse
EX_BE_N[3:0]
Valid Byte
3-4 Cycles
3-4 Cycles
2-16 Cycles
3-4 Cycles
2-17 Cycles
B3756-001
