Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—I2C Bus Interface Unit
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
886
Order Number: 306262-004US
When the I
2
C unit loses arbitration during transmission of the seven address bits and
the processor is not being addressed as a slave device, the I
2
C unit re-sends the
address when the I
2
C bus becomes free. A resend is possible because the IDBR and
ICR registers are not overwritten when arbitration is lost.
If the I
2
C unit loses arbitration because another bus master addresses the processor as
a slave device, the I
2
C unit switches to slave-receive mode and overwrites the original
data in the I
2
C data buffer register. Software can clear the start and re-initiating the
master transaction.
Note:
Software must prevent I
2
C unit from starting a transaction to its own slave address
because such a transaction puts I
2
C unit into an indeterminate state.
Boundary conditions exist for arbitration when an arbitration process is in progress and
a repeated START or STOP condition is transmitted on the I
2
C bus. To prevent errors,
the I
2
C unit, acting as a master, provides for the following sequences:
• No arbitration takes place between a repeated START condition and a data bit
• No arbitration takes place between a data bit and a STOP condition
• No arbitration takes place between a repeated START condition and a STOP
condition
These situations arise only when different masters write the same data to the same
target slave simultaneously and arbitration is not resolved after the first data byte
transfer.
Note:
Typically, software is responsible for ensuring arbitration is lost soon after the
transaction begins. For example, the protocol might insist that all masters transmit
their I
2
C address as the first data byte of any transaction ensuring arbitration is ended.
A restart is then sent to begin a valid data transfer (the slave can then discard the
master’s address).
21.5.5
Master Operations
When software initiates a read or write on the I
2
C bus, the I
2
C unit transitions from the
default slave-receive mode to master-transmit mode. The start pulse is sent followed
by the 7-bit slave address and the R/W# bit. After the master receives an
acknowledge, the I
2
C unit has the option of two master modes:
• Master-Transmit — The IXP45X/IXP46X network processors write data
• Master-Receive — The IXP45X/IXP46X network processors read data
The CPU initiates a master transaction by writing to the ICR register. Data is read and
written from the I
2
C unit through the memory-mapped registers.
describes the I
2
C Bus Interface Unit responsibilities as a master device.