Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Develepor’s Manual
Order Number: 306262-004US
529
PCI Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
enable/disable certain bus signalling characteristics depending on the capabilities of the
devices on the bus. The PCI Controller supports bus configuration both as a host
performing configuration transactions, and as a non-host responding to configuration
transactions from an external agent.
In non-host mode, select registers must be initialized by the Intel XScale processor
before the PCI Controller can respond to PCI configuration cycles from an external
agent. The Subsystem ID and Subsystem Vendor ID are two such registers. The
Initialization Complete bit in the control and status register, when cleared, forces a
retry on the PCI bus in response to configuration cycles. This bit is cleared at reset thus
holding off configuration by an external agent until the PCI Controller configuration
registers are properly initialized. When the Intel XScale processor has completed its
initialization of the necessary registers, it sets the bit to allow PCI configuration to
proceed. A special test mode, indicated by a logic 0 level on the exp_pcitest input port,
overrides this process and tells the PCI Controller to respond to PCI configuration cycles
regardless of the state of Initialization Complete.
When the Intel XScale processor is the PCI host performing system configuration, it is
responsible for setting up the PCI Controller configuration registers as well as those of
all the other devices on the bus. To support this, access to local PCI configuration
registers is provided via a CSR-based configuration access port as described in
Accesses of Local PCI Configuration Registers” on page 534
. Likewise, configuration
read/write cycles can be generated on the PCI bus using a CSR-based PCI access port
as described in
“AHB Non-Prefetch PCI Accesses” on page 535
.
10.3.2.6
PCI Pad Drive Strength Compensation Support
The PCI Core supports PCI pad strength compensation via the exp_rcomp_complete
input. When exp_rcomp_complete is at a logic 0 state, the PCI Core Initiator and Target
interfaces will be inhibited from bus operations thus preventing any switching activity
on the PCI bus from this device. In addition, the PCI arbiter grant outputs
pcc_gnt_n[3:0] will remain in the de-asserted state regardless of the state of the
request inputs. This feature allows an external drive strength compensation circuit to
inhibit any switching of the PCI output drivers until an optimum drive for the PCI pads
can be determined based on temperature and voltage levels on the die. When this drive
is determined, exp_rcomp_complete is asserted to a logic 1 state to allow normal PCI
functioning of the PCI Core.
10.3.2.6.1
Effect on Initiator Interface
When exp_rcomp_complete is logic 0, the PCI Controller Initiator interface is inhibited
from starting a PCI master cycle that may be queued in the Initiator Request FIFO. The
PCI bus request is not asserted. When exp_rcomp_complete is a logic 1, normal
operation of the Initiator Interface is enabled. If one or more requests is waiting in the
Request FIFO when exp_rcomp_complete changes state from 0 to 1, those requests
will be processed in a normal manner.
10.3.2.6.2
Effect on Target Interface
When exp_rcomp_complete is logic 0, the PCI Controller Target interface is inhibited
from responding to PCI cycles initiated from PCI masters. The interface will not drive
any PCI signals and the cycle will terminate with a Master Abort. When
exp_rcomp_complete asserts to a logic 1, the Target Interface will respond normally to
the next PCI cycle that targets this device, usually a Configuration Read.
