Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Reference Number: 306262-004US
273
UTOPIA Level 2—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
The Receive Module will poll a programmable number of physical interfaces, as defined
by the Receive Address Range (RXADDRRANGE) register. If three physical interfaces
are connected to the UTOPIA Level 2 interface, a value of two can be programmed into
the Receive Address Range (RXADDRRANGE) register by the Network Processor Engine
core. The polling will always begin at address 0 and poll sequentially to the value
contained in the Receive Address Range (RXADDRRANGE) register. If, for example, a
two was programmed into the Receive Address Range (RXADDRRANGE) register, the
external physical interfaces would have to be configured to respond to the first three
physical addresses produced by the UTOPIA Level 2 UTP_IP_ADDR signals.
To allow the most flexibility a logical address to physical address table is provided. The
look-up table makes it possible for the three addresses that were called out above not
to be in sequential order.
For example, the following logical to physical address map could be used for the above
example of three physical interfaces.
• Logical Address 0 => Physical Address 3 => UTP_IP_ADDR lines = “00011”
• Logical Address 1 => Physical Address 5 => UTP_IP_ADDR lines = “00101”
• Logical Address 2 => Physical Address 7 => UTP_IP_ADDR lines = “00111”
Once the physical address is driven to all physical interfaces using the UTP_IP_ADDR
signals. The physical interface that is prepared to send a cell — and configured to the
address signals that match the values contained on the UTP_IP_ADDR signals —
responds to the UTOPIA Level 2 Interface on the IXP45X/IXP46X network processors by
driving the UTP_IP_FCI (also known as RX_EMPTY_N/RX_CLAV) signal, to inform the
UTOPIA Level 2 Interface that the physical interface is ready to send a cell.
The Receive Port Status (RXPORTSTAT) register, contained within the Receive Module,
stores the polling result for each of the physical interfaces. The UTOPIA Level 2
hardware uses the values — stored in the Receive Port Status (RXPORTSTAT) Register
— to determine the physical interface the received cell originated from. The Receive
Module will store the received cell along with the physical interface address that the cell
was received from into the Receive FIFO with some basic filtering capability if desired.
The Network Processor Engine will then read the address from which the cell originated
and then the cell.
The Receive Module performs an optional, cell-level filtering that may cause a cell to be
discarded prior to being placed into the Receive FIFO. Some of these features can be
enabled or disabled include:
• Received cells that are too short are discarded
• Excess bytes of received cells that are too long are discard
• Detection of HEC errors in the cell header causes the cell to be discarded (Can be
enabled/disabled)
• Detection of idle cells will be discarded (Can be enabled/disabled. The definition of
an idle cell is programmable by setting the appropriate values in the Receive Define
Idle [RxDefineIdle] registers)
As the Receive Module is placing data into the Receive FIFO, the header information is
being passed to the Receive Pre-Hash Unit.
The UTOPIA Coprocessor Receive Pre-Hash Module provides a mechanism for allowing
incoming UTOPIA cells to have the ATM header looked up in a hash table to achieve
faster address recognition. The hash unit takes the incoming ATM header, combines it
with the arriving port information, and produces a header that can be read by the
Network Processor Engine core. The Receive Pre-Hash Function can be enabled or
disabled and can be used in single-PHY or multiple-PHY modes of operation. When used
in single-PHY mode of operation, the port address will always be zero.
