Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Reference Number: 306262-004US
65
Functional Overview—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
2.2.6
Data Cache
The Data Cache (D-Cache) can contain high-use data such as lookup tables and filter
coefficients, allowing the Intel XScale processor access to data at core frequencies. This
prevents stalls caused by multi-cycle accesses to external memory.
The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways
and each way contains a tag address, a cache line (32 bytes with one parity bit per
byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and
one valid bit. For each of the 32 sets, zero through 28 ways can be locked, unlocked,
or used as local SRAM. Unlocked ways are replaceable via a round-robin policy.
The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute
bits within the descriptors, contained in the DTLB of the DMMU, provide significant
control over an enabled D-cache. These bits specify cache operating modes such as
read and write allocate, write-back, write-through, and D-cache versus mini-data cache
targeting.
The D-cache (and mini-data cache) work with the load buffer and pend buffer to
provide “hit-under-miss” capability that allows the Intel XScale processor to access
other data in the cache after a “miss” is encountered. The D-cache (and mini-data
cache) works in conjunction with the write buffer for data that is to be stored to
memory.
2.2.7
Mini-Data Cache
The mini-data cache can contain frequently changing data streams such as MPEG
video, allowing the Intel XScale processor access to data streams at core frequencies.
This prevents stalls caused by multi-cycle accesses to external memory. The mini-data
cache relieves the D-cache of data “thrashing” caused by frequently changing data
streams.
The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains
two ways and each way contains a tag address, a cache line (32 bytes with one parity
bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line),
and a valid bit. The mini-data cache uses a round-robin replacement policy, and cannot
be locked.
The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute
bits contained within a coprocessor register specify operating modes write and/or read
allocate, write-back, and write-through.
The mini-data cache (and D-cache) work with the load buffer and pend buffer to
provide “hit-under-miss” capability that allows the Intel XScale processor to access
other data in the cache after a “miss” is encountered. The mini-data cache (and D-
cache) works in conjunction with the write buffer for data that is to be stored to
memory.
2.2.8
Fill Buffer and Pend Buffer
The four-entry fill buffer (FB) works with the Intel XScale processor to hold non-
cacheable loads until the bus controller can act on them. The FB and the four-entry
pend buffer (PB) work with the D-cache and mini-data cache to provide “hit-under-
miss” capability, allowing the Intel XScale processor to seek other data in the caches
while “miss” data is being fetched from memory.
The FB can contain up to four unique “miss” addresses (logical), allowing four “misses”
before the Intel XScale processor is stalled. The PB holds up to four addresses (logical)
for additional “misses” to those addresses that are already in the FB. A coprocessor
register can specify draining of the fill and pend (write) buffers.
