Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
707
Expansion Bus Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
These configuration bits are made available to the system as outputs from the
Expansion bus controller block. With the exception of bits 23, 22 and 21, which are
read only, all other bits may be written and read from the AHB. However software
should only modify the value of MEM_MAP (bit 31) and leave all other values as the
captured value.
Register Name:
EXP_CNFG0
Hex Offset Address:
0XC4000020
Reset Hex Value:
0x80XXXXXX
Register
Description:
Configuration Register #0
Access: Read/Write.
31 30
24 23 22 21 20
17 16 15
10 9
8
7
6
5
4
3
2
1
0
MEM_MAP
(Reserved)
Clock Set
Customer
(Reserved)
IOW
A
IT
_
C
S0
EX
P_MED
_
DRIVE
US
B CLOC
k
32_FLASH
EXP
_
AR
B
EX
P_
DR
IV
E
PC
I_ CLK
PCI_A
R
B
PC
I_ HO
S
T
8/16
Table 229.
Configuration Register 0 Description (Sheet 1 of 2)
Bit
Name
Reset Value
Description
31
MEM_MAP
1
Location of Expansion Bus in memory map space:
0 = Located at “50000000” (normal mode)
1 = Located at “00000000” (boot mode)
30:24
(Reserved)
0x0
(Reserved)
23:21
Intel XScale
®
Processor
Clock Set[2:0]
EX_ADDR[23:
21]
Allow a slower Intel XScale processor clock speed to override
device fuse settings. However cannot be used to over clock core
speed. Refer to
Table 230, “Setting The Intel XScale® Processor
for additional details.
20:17
Customer
EX_ADDR[20:
17]
Customer defined bits.
16:11
(Reserved)
EX_ADDR[16:
11]
(Reserved)
10
IOWAIT_CS0
EX_ADDR[10]
1 = EX_IOWAIT_N is sampled during the read/write Expansion bus
cycles as defined in
Section 12.4.1.5, “Using I/O Wait” on
for Chip Select 0.
0 = EX_IOWAIT_N is ignored for read and write cycles to Chip
select 0 if EXP_TIMING_CS0 is configured to Intel mode. Typically,
IOWAIT_CS0 must be pulled down to Vss when attaching a
Synchronous Intel StrataFlash on Chip select 0 since the default
mode for EXP_TIMING_CS0 is Intel mode and EX_IOWAIT_N is an
unknown value for Synchronous Intel StrataFlash. If the board
does not connect the Synchronous Intel StrataFlash WAIT pin to
EX_WAIT_N (and the board guarantees EX_IOWAIT_N is pulled
up), the value of IOWAIT_CS0 is a don’t care since EX_IOWAIT_N
will not be asserted. When EXP_TIMING_CS0 is reconfigured to
Intel Synchronous mode during boot-up (for Synchronous Intel
chips), the Expansion bus controller ignores EX_IOWAIT_N during
read and write cycles since the WAIT functionality is determined
from the EXP_SYNCINTEL_COUNT and EXP_TIMING_CS registers.
9
EXP_MEM_DRIVE
EX_ADDR[9]
Refer to the table found in EXP_DRIVE bit (bit 5) of this register.
