Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
705
Expansion Bus Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
12.5.7
Timing and Control Registers for Chip Select 6
12.5.8
Timing and Control Registers for Chip Select 7
Register Name:
EXP_TIMING_CS6
Hex Offset Address:
0XC4000018
Reset Hex Value:
CS6:
0x00000000
Register
Description:
Timing and Control Registers
Access: Read/Write.
31 30 29 28 27 26 25
22 21 20 19
16 15 14 13
9
8
7
6
5
4
3
2
1
0
CS
x_E
N
PA
R
_
E
N
T1
T2
T3
T4
T5
CY
CLE
_
TY
PE
CNFG[4:0]
S
ync_Inte
l
EXP
_
C
H
IP
BYTE
_RD16
HRD
Y
_PO
L
MU
X
_
E
N
SP
LT
_EN
WORD_E
N
WR_EN
BYTE
_EN
Register Name:
EXP_TIMING_CS7
Hex Offset Address:
0XC400001C
Reset Hex Value:
CS7:
0x00000000
Register
Description:
Timing and Control Registers
Access: Read/Write.
31 30 29 28 27 26 25
22 21 20 19
16 15 14 13
9
8
7
6
5
4
3
2
1
0
CS
x_E
N
PA
R
_
E
N
T1
T2
T3
T4
T5
CY
CLE
_
TY
PE
CNFG[4:0]
Sy
n
c_
In
te
l
EX
P_
C
H
IP
BY
T
E
_
R
D
1
6
HRDY_P
OL
MU
X
_
E
N
SP
LT
_EN
WORD_EN
WR_EN
BY
TE_E
N
Table 228.
Bit Level Definition for each of the Timing and Control Registers (Sheet 1 of 2)
Bits
Name
Description
31
CSx_EN
0 = Chip Select x disabled
1 = Chip Select x enabled
30
PAR_EN
0 = Parity is not generated or compared
1 = Parity is generated and compared
Parity is only supported for Intel, Motorola, and Micron ZBT
modes.
29:28
T1 – Address timing
00 = Generate normal address phase timing
01 - 11 = Extend address phase by 1 - 3 clocks
27:26
T2 – Setup / Chip Select
Timing
00 = Generate normal setup phase timing
01 - 11 = Extend setup phase by 1 - 3 clocks
25:22
T3 – Strobe Timing
0000 = Generate normal strobe phase timing
0001-1111 = Extend strobe phase by 1 - 15 clocks
21:20
T4 – Hold Timing
00 = Generate normal hold phase timing
01 - 11 = Extend hold phase by 1 - 3 clocks
19:16
T5 – Recovery Timing
0000 = Generate normal recovery phase timing
0001-1111 = Extend recovery phase by 1 - 15 clocks
