Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
611
Memory Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
1. Each of the MCU inbound memory transaction ports decodes the address to
determine if the transaction should be claimed.
— If the address falls in the DDRI SDRAM address range indicated by the SDBR,
SBR0, SBR1, and S32SR the MCU claims the transaction and latches the
transaction in the respective memory transaction queue.
2. Once the MARB selects the highest priority transaction from the memory
transaction queues, it forwards the transaction to the DDRI SDRAM control block.
The DDRI SDRAM Control Block decodes the address to determine whether or not
any of the open pages are hit.
— The ECC logic generates the ECC code for the data to be written.
A write that misses the open page encounters a miss penalty because the currently
open page needs to be closed before the write can be issued to the new page. Refer to
“Page Hit/Miss Determination” on page 595
for the paging algorithm details. If a page
hit occurs, steps 3-4 are skipped by the MCU.
3. The DDRI SDRAM Control Block closes the currently open page by issuing a
precharge
command to the currently open row.
— The DDRI SDRAM Control Block waits T
rp
cycles after the precharge before
issuing the
row-activate
command for the new write transaction.
4. The
row-activate
command enables the appropriate row.
— The DDRI SDRAM Control Block asserts DDRI_RAS_N, de-asserts DDRI_WE_N,
and drives the row address on DDRI_MA[13:0].
5. After T
rcd
cycles in the case of a page miss, the DDRI SDRAM Control Block asserts
DDRI_CAS_N, asserts DDRI_WE_N, and places the column address on
DDRI_MA[13:0]. This initiates the burst write cycle. The DDRI SDRAM Control
Block drives the data to be written and its ECC code to the DDRI SDRAM devices.
• The DDRI SDRAM Control Block drives the new data to the corresponding memory
transaction queue each cycle until the transaction is completed with the byte count
expiring, or the transaction is interrupted if preemption conditions are met.
• For each burst issued, the DDRI SDRAM Control Block increments the address by
four.
• If ECC is enabled, when the data to write is not aligned on an 4 byte boundary for
32-bit data bus width, the DDRI SDRAM Control Block will perform a read-modify-
write of the entire 4 byte aligned double-word for 32-bit data bus width and
incorporate the new data while regenerating ECC.
Note:
Even though the data is not written while the DDRI SDRAM Control Block asserts
DDRI_DM[4:0], the burst cycle will complete.
The MCU supports optimized performance for random address transactions. This
optimization eliminates the need of the DDRI SDRAM Control Block to issue the
transaction command to the DDRI array if the previous transaction is the same type
(read or write). In addition, the DDRI SDRAM Control Block supports pipelining of
transactions which allows the column address of the next transaction to be issued
before the current transaction’s data transfer is completed by the DDRI SDRAM
devices. These optimizations are illustrated in
transactions.
