Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—USB 1.1 Device
Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
304
Order Number: 306262-004US
8.5.7
UDC Endpoint 5 Control/Status Register
(UDCCS5)
The UDC Endpoint 5 Control Status Register contains six bits that are used to operate
Endpoint 5, an Interrupt IN endpoint.
8.5.7.1
Transmit FIFO Service (TFS)
The transmit FIFO service bit is set if the FIFO does not contain any data bytes and
UDCCS5[TSP] is not set.
Register Name:
UDCCS4
Hex Offset Address:
0x C800B020
Reset Hex Value:
0x00000000
Register
Description:
Universal Serial Bus Device Controller Endpoint 4 Control and Status Register
Access: Read/Write
Bits
31
8
7
6
5
4
3
2
1
0
(Reserved)
RSP
RNE
(Rsvd
)
(Rsvd
)
(Rsvd
)
RO
F
RP
C
RFS
X
0
0
0
0
0
0
0
0
Resets (Above)
Register
UDCCS4
Bits
Name
Description
31:8
Reserved for future use.
7
RSP
Receive short packet (read only).
1 = Short packet received and ready for reading.
6
RNE
Receive FIFO not empty (read-only).
0 = Receive FIFO empty.
1 = Receive FIFO not empty.
5
(Reserved). Always reads 0.
4
(Reserved). Always reads 0.
3
(Reserved)
2
ROF
Receive overflow (read/write 1 to clear).
1 = Isochronous data packets are being dropped from the host because the
receiver is full.
1
RPC
Receive packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Receive packet has been received and error/status bits are valid.
0
RFS
Receive FIFO service (read-only).
0 = Receive FIFO has less than 1 data packet.
1 = Receive FIFO has 1 or more data packets.
