Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Memory Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
620
Order Number: 306262-004US
11.2.3.3
ECC Checking
If enabled, the ECC logic uses the following ECC read algorithm. This algorithm corrects
the data before it is driven onto the internal bus.
The ECC algorithm for a read transaction is:
When the MCU reads the ECC code from the memory subsystem, it is compared
(XORed) with an ECC that the MCU generates from the data read from the memory.
The result is called the syndrome.
shows how the MCU decodes the
syndrome for DDRI SDRAM read cycles.
shows how the data flows through the ECC hardware for a read transaction.
Read 64/32-bit data and 8-bit ECC (For the IXP45X/IXP46X network processors,32 bit
read data is zero extended to 64 bits)
Compute the syndrome by passing the 64-bit data through the G-Matrix and XORing
the 8-bit result with the 8-bit ECC
if the syndrome <> 0 {ECC Error}
Look up in H-matrix to determine error type
Register the address where the error occurred
if error is correctable {single bit}
if single-bit error correction is enabled
Correct data
Send corrected data to internal bus
if single bit error reporting is enabled
Interrupt core for software scrubbing
else {uncorrectable}
if the read cycle is
not
part of a RMW cycle {read}
Target-Abort the Internal Bus read transaction.
else {write requiring RMW}
Merge the new data portion with the read data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
if multi-bit error reporting is enabled
Interrupt the core for uncorrectable error
Table 213.
Syndrome Decoding
Error Type
Symptom
None
The syndrome is 0000 0000.
Single-Bit
Use the H-Matrix in
to determine which bit the MCU will invert to fix the error.
Multi-Bit
If the Syndrome does not match an 8-bit value in the H-matrix, the error is uncorrectable.
