Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Develepor’s Manual
Order Number: 306262-004US
541
PCI Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
10.3.4
Data Byte Alignment and Addressing — PCI Endianness
The PCI Local Bus Specification, Rev. 2.2 defines the byte-addressing convention on the
PCI Bus as little-endian. Since the byte addressing convention on the PCI bus is little-
endian and the convention used on the AHB bus is big-endian, data passing from the
PCI Core FIFOs to and from the AHB bus can go through an optional CSR-bit controlled
byte lane reversal. The AHB bus interfaces can also be configured to operate in either
big-endian or little-endian addressing conventions.
As shown in
, when an external PCI device accesses an AHB address with the
AHB in big-endian mode (pci_csr.ABE = 1), the pci_csr.PDS (PCI Data Swap) bit
controls the byte lane swapping between the two busses. When pci_csr.PDS is 1, the
PCI data bytes are treated as little-endian addressed and are swapped to the
corresponding big-endian byte lanes of the AHB bus. In the figure, PCI bytes are
numbered according to the corresponding PCI byte enables and AHB bytes are
numbered according to the corresponding byte address on the AHB bus. For example, a
PCI write with byte enable 2 asserted and pci_csr.PDS = 1 will produce an AHB byte
write with AHB address bits [1:0] = 10b. When pci_csr.PDS is 0, the PCI data bytes are
treated as big-endian addresses and are not swapped. In this case, a PCI write with PCI
byte enable 2 asserted will produce an AHB byte write with AHB address bits [1:0] =
01b.
shows the byte alignment in AHB little-endian mode (pci_csr.ABE = 0).
