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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
821
Operating System Timer—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
= 20ns * 26 * 24 = 12.48us
If it is desirable to pause the timer, then use the tim0_pause_en to halt counting
4. ost_tim0_cfg <= 0x0F This will set tim0_pause_en
To enable the counting such that the counter continues from its paused value
5. ost_tim0_pre <= 0x19 This is a refresh write that is necessary for the prescale to
properly work.
6. ost_tim0_cfg <= 0x07 Clear tim0_pause_en
If no prescaler is used, step 5 is not necessary to do.
18.4.4
Clock Prescale
Each timer except the watch dog is provided with a programmable prescaler that
divides the input clock with a 16-bit value. The input clock can be either the APB
system clock or a 20-ns version of it (3/4scale). By default all timers use the apb clock.
The 16-bit prescale value ranges from divide by 2 to 65,536, and results in a new clock
enable available for the timers that ranges from 33.33 MHz down to 1017.26 Hz, the
divider is a divide by N+1, where N={0,1,2,3...}. The value for the new available clock
enable is written in the internal register for the desired timer, the new value is updated
on the next positive edge of pclk.
18.5
Detailed Register Descriptions
The registers are accessible via the APB bus interface.
Table 264.
Register Legend
Attribute
Legend
Attribute
Legend
RV
Reserved
RC
Read Clear
PR
Preserved
RO
Read Only
RS
Read/Set
WO
Write Only
RW
Read/Write
NA
Not Accessible
RW1C
Normal Read
Write ‘1’ to clear
RW1S
Normal Read
Write ‘1’ to set
Table 265.
Register Summary
Address
Register Name
Description
Reset Value
Attribute
Counter
type
RW
Up
RO
Down
“General-Purpose Timer 0 Reload”
RW
n/a
RO
Down
“General-Purpose Timer 1 Reload”
RW
n/a
RW
†
Down
“ost_wdog_enab” “Watchdog Enable Register”
RW
†
n/a
RW
n/a
RW1C
n/a
†
Only through watchdog protection mechanism