Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
683
Expansion Bus Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
EX_SLAVE_CS_N but deasserting EX_RD_N for at least one cycle. The new transfer
starts when EX_RD_N is asserted and the Expansion bus controller will always assert
EX_WAIT_N one cycle later.
For 8-word read transfers, the Expansion bus protocol begins the same way as a 1-
word transfer, however data words 2 through 8 will never assert EX_WAIT_N. Typically
the master increments EX_ADDR[4:2] by 0x1 for each data cycle until all 8 words are
transferred, however this is not mandatory. The Expansion bus controller only monitors
EX_ADDR[4:2] to determine which word is being transferred. For 8-word data
transfers, external masters can also insert wait states for each word of the data
transfer by not incrementing EX_ADDR every cycle. Once all 8 words have been
transferred the master can deassert EX_SLAVE_CS_N. For 8-word reads, the master
can also end the burst early by deasserting EX_SLAVE_CS_N anytime after EX_WAIT_N
is deasserted. The master can then re-start the 8-word read by re-asserting
EX_SLAVE_CS_N, however the Expansion bus controller will not assert EX_WAIT_N if
EX_ADDR[4:2] is not equal to 0x0. This will significantly improve the performance of 8-
word reads, since the data is already present in the Expansion bus data fifo.
The master can also choose to do back-to-back 8-word reads by leaving
EX_SLAVE_CS_N asserted but deasserting EX_RD_N for at least one cycle. The
Expansion bus controller will monitor EX_ADDR[4:2] to determine when a new 8-word
burst has started and assert EX_WAIT_N one cycle after the assertion of EX_RD_N.
EX_WAIT_N will be deasserted when the Expansion bus controller has received the
data from the AHB.
The Expansion bus controller does not support back-to-back reads of different burst
lengths; the master must always deassert EX_SLAVE_CS_N between different burst
length reads. Additionally the Expansion bus controller does not support back-to-back
reads followed by writes or writes followed by reads. Unpredictable operation will result
if EX_BURST is changed while EX_SLAVE_CS_N is asserted for reads or writes.
Write transactions start with EX_SLAVE_CS_N and EX_WR_N asserted. The Expansion
bus controller ignores EX_ADDR on the first cycle of a new write transfer. For write
transactions the Expansion bus controller will need to assert EX_WAIT_N only if its
write queue is busy completing a previous write transfer. If the Expansion bus inbound
queue is free, the Expansion bus controller will not assert EX_WAIT_N for the current
write transfer. Once the master detects that EX_WAIT_N is deasserted, the master can
deassert EX_SLAVE_CS_N for 1-word/sub-word data transfers. The master can also
start a new write transfer by leaving EX_SLAVE_CS_N asserted but deasserting
EX_WR_N for at least one cycle. The new transfer starts when EX_WR_N is asserted
and the Expansion bus controller will assert EX_WAIT_N one cycle later if its busy
completing the previous write.
For 8-word write transfers, the Expansion bus protocol begins the same way as a 1-
word transfer. The external master cannot start the 2nd address cycle until EX_WAIT_N
is sampled deasserted. Since it takes one cycle for the Expansion bus controller to drive
EX_WAIT_N, the first address cycle will always be at least two cycles. However, data
words 2 through 8 will never assert EX_WAIT_N. For 8-word writes, the master
increments EX_ADDR[4:2] by 0x1 for each data cycle until all 8 words are transferred.
The Expansion bus controller monitors EX_ADDR[4:2] to determine which word is being
transferred. The Expansion bus controller samples EX_DATA when EX_ADDR[4:2]
increments, a NOP cycle is inserted after a data state, or when EX_SLAVE_CS_N is
deasserted. For 8-word data transfers, external masters can also insert wait states for
each word of the data transfer by not incrementing EX_ADDR every cycle, however the
setup and hold times must be met for EX_ADDR on every cycle. For 8-word writes, the
master can temporarily end the burst anytime after EX_WAIT_N is deasserted by
deasserting EX_SLAVE_CS_N. The master must re-start the 8-word write by re-
asserting EX_SLAVE_CS_N to complete the burst, however the Expansion bus
controller will not assert EX_WAIT_N if EX_ADDR[4:2] is not equal to 0x0. The
Expansion bus controller will only send the 8-word write data to the AHB when
EX_ADDR[4:2] = 0x7 and the master has finished the transfer by deasserting
