Intel IXP45X, Developer'S Manual

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Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006 Developer’s Manual
Order Number: 306262-004US 591
Memory Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Note: DDRI SDRAM memory space must be aligned to a 32-Mbyte boundary and must never
cross a 2-Gbyte boundary.
Note: With 32-bit DDRI SDRAM attached to the IXP45X/IXP46X network processors, all DDRI
SDRAM memory space behaves as 32-bit DDRI SDRAM and the value in S32SR is
ignored.
The base register defines the upper seven address bits of the DDRI SDRAM memory
space. The boundary registers define the address limits for each DDRI SDRAM bank in
32 Mbyte granularity. Table 205 defines the conditions which must be satisfied to
activate a DDRI SDRAM memory bank.
Table 206 shows the correct programming values for the DDRI SDRAM Bank Size
encoding. These Bank Size Codes are used in the calculation of the DDRI SDRAM
boundary registers programming values. Equation 1 and Equation 2 show the required
equations to calculate the programming values for the DDRI SDRAM boundary
registers.
Note: For IXP45X/IXP46X network processors, both banks must be programmed to be the
same size.
Table 204. DDRI SDRAM Address Register Summary
DDRI SDRAM Address Register Definition
DDRI SDRAM Base Register (SDBR)
The lowest address for DDRI SDRAM memory space aligned to a
32-Mbyte boundary.
DDRI SDRAM Boundary Register 0 (SBR0)
The upper address boundary for bank 0 of DDRI SDRAM memory
space. SBR0 must be greater than or equal to the value of
SDBR[30:25].
DDRI SDRAM Boundary Register 1 (SBR1)
The upper address boundary for bank 1 of DDRI SDRAM memory
space. SBR1 must be greater than or equal to SBR0.
DDRI SDRAM 32-Bit Size Register (S32SR)
The size for the memory space to operate as 32-bit memory (in
MBs). S32SR must be less than, or equal to 1/2 of bank 0 size.
Ignored with a 32-bit data bus width.
Table 205. Address Decoding for DDRI SDRAM Memory Banks
Condition DDRI SDRAM Bank Selected
ADDR[31] is not equal to the SDBR[31] None
ADDR[31] is equal to the SDBR[31]
AD[30:25] is greater than or equal to the SDBR[30:25]
AD[30:25] is less than the value in SBR0
Bank 0
ADDR[31] is equal to the SDBR[31]
AD[30:25] is greater than or equal to the value in SBR0
AD[30:25] is less than the value in SBR1
Bank 1
ADDR[31] is equal to the SDBR[31]
AD[30:25] is greater than or equal to the value in SBR1
None
Table 206. Programming Codes for the DDRI SDRAM Bank Size
Bank Size Code Bank Size Code
Empty 00H 256 Mbyte 08H
32 Mbyte 01H 512 Mbyte 10H
64 Mbyte 02H 1 Gbyte 20H
128 Mbyte 04H