Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
637
Memory Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
11.6.4
DDRI SDRAM Base Register SDBR
This register indicates the beginning of SDRAM space. See
SDRAM Bank Sizes and Configurations” on page 590
for usage details. There can be
two contiguous physical banks defined by SBR0 and SBR1 in the DDRI SDRAM
subsystem starting at this address.
Note:
DDRI SDRAM memory space must never cross a 2 Gbyte boundary.
Note:
This register should be read back after being written, before the Intel XScale processor
performs transactions which address the DDRI SDRAM.
Register Name:
SDRAM Base Register - SDBR
Hex Offset Address:
CC00 E50CH
Reset Hex Value:
0x0000 0000H
Register Description:
SDRAM Base Register
Access: See below.
31
25 24
00
(Reserved)
Register
SDRAM Base Register - SDBR
Bits
Name
Description
Default
Access
31:2
5
SDRAM Base Address: These bits define the upper seven bits of the
DDRI SDRAM base address. These seven bits are compared with
ADDR[31:25] to determine if the internal bus transaction hits SDRAM
memory space. See
00H
RW
24:0
0
(Reserved)
000000H
RO