Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Expansion Bus
Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
686
Order Number: 306262-004US
Since the AC timings for EX_WAIT_N is critical, the Expansion bus controller will only
use EX_SLAVE_CS_N, EX_WR_N, EX_RD_N, EX_ADDR[4:2], EX_BURST, and the
Expansion bus controller internal state to determine if it needs to assert EX_WAIT_N.
The tri-state enable for EX_DATA pins should be based upon EX_SLAVE_CS_N and
EX_RD_N.
For inbound transfers, the AHB address is determined from EX_ADDR and the
EXP_INBOUND_ADDR register and is described in detail in
. For reads the master must drive EX_ADDR on the cycle that
EX_SLAVE_CS_N is asserted. For 1-word or sub-word write data transfers, EX_ADDR
is only sampled one cycle before EX_SLAVE_CS_N is deasserted. For 8-word writes, the
master must drive EX_ADDR the cycle after EX_SLAVE_CS_N is asserted. The AHB bus
is configured to be big-endian. The Expansion bus controller uses EX_BE_N to generate
sub-word addresses on writes. Sub-word reads are unsupported and the AHB
address[1:0] is always 0x0 for reads.
Inbound transfers to the AHB bus can be byte swapped based upon the value of
EXP_BYTE_SWAP_EN. If enabled, BYTE 0 is swapped with BYTE 3 and BYTE 1 is
swapped with BYTE 2. The byte swapping occurs for all accesses except accesses to
Expansion bus MMRs.
12.4.2.1
Parity
The Expansion bus controller generates even or odd parity for each byte returned to
EX_DATA and compares parity for each byte written on EX_DATA, if INPAR_EN is set in
the EXP_MST_CONTROL register. EX_PARITY is transferred in the same clock cycle in
which EX_DATA is transferred. If a write compare results in a parity mismatch on
EX_PARITY, the AHB address is logged in the EXP_PARITY_STATUS and InErrorSts is
set. Even if there is a parity error, the write data is still transferred to the AHB interface.
Exp_parity_error will be asserted by the Expansion bus controller during a parity error
and an interrupt will be generated if enabled in the interrupt controller.
Exp_parity_error will remain asserted until software clears the EXP_PARITY_STATUS
register.
Even parity is defined as the number of 1’s on EX_DATA[7:0] and EX_PARITY[0] must
be an even number. Parity for the 2nd byte of EX_DATA is generated on EX_PARITY[1];
the 3rd byte of EX_DATA is generated on EX_PARITY[2], and the 4th byte of EX_DATA
is generated on EX_PARITY[3]. For byte and halfword writes the Expansion bus
controller will not generate or compare parity on byte enables that are not asserted. If
INPAR_EN is cleared, the Expansion bus controller doesn’t generate or compare parity
and EX_PARITY should not toggle to conserve power. Odd parity can be enabled by
setting OddPar in the EXP_MST_CONTROL register and is equivalent to the inverted
value of even parity.
If the Expansion bus controller receives an error response on AHB HRESP during a read
transfer, the Expansion bus controller will drive 0x0 on EX_DATA and generate incorrect
parity by inverting EX_PARITY for the offending word/words. If the Expansion bus
controller is reading from DDRI SDRAM and un-correctable ECC error occurs, the
Expansion bus controller will also generate incorrect parity on EX_PARITY.
12.4.3
Arbitration
The Expansion bus controller provides arbitration between IXP45X/IXP46X network
processors and up to four external masters. An external arbiter can also be used, if
desired. The external arbiter is enable by the EX_ADDR driving bit 6 of EX_ADDR to
logic 0.
