Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—HSS Coprocessor
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
728
Reference Number: 004US
, the first NPE Core write to the LUT will be to position 1, the last write will
be to position 8.
Each FIFO controller will communicate to the arbitrator any full RX buffers and any
empty TX buffers, when the TX FIFO (both buffers) is empty (under-run), and when the
RX FIFO (2 buffers) is full (over-run). It is up to the NPE Core to prevent the TX FIFO
from underflowing and prevent the RX FIFO from overflowing.
In the case where the HSS has finished transmitting the first TX buffer and the second
buffer is due for transmission, the second buffer must have been completely filled
previously by the NPE Core to prevent underflow. The same system applies to the RX
FIFOs.
In the case of 1 or more simultaneous RX voice ‘A’ buffers becoming full, the arbitrator
will generate the ‘hss_rx_va_full’ signal as needed. The NPE Core will issue the
HSSrdRxVaCond instruction (result indicates which FIFO/core activated the signal) and
Figure 165. Look-Up Table Organization
B4232-01
0-15
15-31
32-47
48-63
64-79
80-95
96-111
112-127
quad MVIP
dual MVIP
E1/T1
25
6
27 29 31
17 19 21 23
9
11 13 15
1
3
5
7
24 26 28 30
16 18 20
22
8
10 12 14
0
2
4
Number indicates the location on the psm_data bus (31=MSb)
Transmitted/received first
Transmitted/received last
Timeslot number
Type Bits
___________
00 = Unassigned
01 = HDLC
11 = Voice
10 = 56K mode
Lookup table size is dependent
on the protocol used
position 1
position 8
