Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
69
Intel XScale
®
Processor—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
3.0
Intel XScale
®
Processor
This chapter provides functional descriptions of the Intel XScale
®
Processor.
3.1
Memory Management Unit
This section describes the memory management unit implemented in the Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors.
The Intel XScale
®
Processor implements the Memory Management Unit (MMU)
Architecture specified in the ARM* Architecture Reference Manual. To accelerate
virtual-to-physical address translation, Intel XScale processor uses both an instruction
Translation Look-Aside Buffer (TLB) and a data TLB to cache the latest translations.
Each TLB holds 32 entries and is fully associative.
Not only do the TLBs contain the translated addresses, but also the access rights for
memory references.
If an instruction or data TLB miss occurs, a hardware translation-table-walking
mechanism is invoked to translate the virtual address to a physical address. Once
translated, the physical address is placed in the TLB along with the access rights and
attributes of the page or section. These translations can also be locked down in either
TLB to guarantee the performance of critical routines.
For more information, refer to
The Intel XScale processor allows system software to associate various attributes with
regions of memory:
• Cacheable
• Bufferable
• Line-allocate policy
• Write policy
• I/O
• Mini data cache
• Coalescing
For a description of page attributes, see
“Cacheable (C), Bufferable (B), and eXtension
. For information on where these attributes have been mapped in
the MMU descriptors, see
“New Page Attributes” on page 175
.
Note:
The virtual address with which the TLBs are accessed may be remapped by the PID
register. For a description of the PID register, see
.