Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
583
Memory Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
3. The MAB some time later sends the write request to the MCU core which performs
the write to DDR memory location A2 (any DDR memory location).
4. Master on the expansion bus writes a pointer to the just written data (destined for
Advanced Queue Manager) to the expansion bus controller's internal queue.
5. Expansion bus controller initiates a South AHB write to the Advanced Queue
Manager.
6. Intel XScale processor reads pointer from Advanced Queue Manager
7. Intel XScale processor writes a timestamp to location A2.
In the above example the Expansion Bus write may complete before or after the Intel
XScale processor write.
In this example the Advanced Queue Manager is not required to have this race
condition. The same condition can be observed using an interrupt to hand control from
an AHB master to the Intel XScale processor.
How to avoid
Any of the following will eliminate the race condition between an AHB master writing to
the same exact DDR memory location that the Intel XScale processor is writing to.
1. Intel XScale processor needs to perform a read before it tries to write to the same
exact DDR memory location. As stated above the MCU core will ensure any writes in the
MAB or BIU will be processed before the read is returned thus ensuring the newest data
is in DDR.
2. The AHB master performs a read of the location before handing control over to the
Intel XScale processor.
3. The AHB master performs a write to a different location before handing control over
to the Intel XScale processor.
4. Disable the BIU MPI port.
No consideration is required if two or more masters write to adjacent memory locations
because each write is destined to it's own memory location and if a read is preformed
the MCU core will ensure the newest data is returned.
