Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
699
Expansion Bus Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
The above timing diagram shows the request and grant lines for two external masters.
The Expansion bus controller owns the bus in cycles 0 and 1. The Expansion controller
must tri-state the shared Expansion bus outputs on or before cycle 3. Master 0 owns
the bus in cycles 3-5 and Master 1 owns the bus in cycles 7-10. In the above example,
master 0 asserts EX_CS_N one cycle after its grant is asserted. Master 1 does not
assert EX_CS_N until two cycles after its grant is asserted. A master can only assert
EX_CS_N/EX_SLAVE_CS_N if its grant was asserted in the previous cycle. In this
example, if master 1 did not assert EX_CS_N/EX_SLAVE_CS_N in cycle 9 it cannot
assert it in cycle 10, since EX_GNT_N[1] was not asserted in cycle 9. A master may
lose its grant in any cycle when GrantRemove = 1, however grant is always asserted for
at least two cycles. When a master loses grant, it stills owns the bus until the current
transfer is complete. The Expansion bus controller monitors EX_CS_N and
EX_SLAVE_CS_N to determine when the transfer is complete. The cycle after all the
chip selects are disabled, the master must tri-state the bus. In this example master 0
must tri-stated the shared Expansion bus pins in cycle 7.
12.4.6.2
Arbitration When GrantRemove Bit in EXP_MST_CONTROL
is Clear
The above timing diagram shows the arbitration protocol when the GrantRemove bit is
clear. Once grant is asserted to the master, that master will not lose grant until one
cycle after its request is deasserted. In the above example, master 0 could start a new
data transfer in cycle 8, however it chose not to start a new transfer. If a new transfer
was started, the arbiter must not assert master 1’s grant in cycle 9 and it must
arbitrate after master 0 is finished with that transfer (and its request is deasserted). If
master 0 started a new transfer in cycle 8, that master may not own the bus after that
transfer completes. In this example master 0 tri-states the Expansion bus in cycle 8.
Typically an external master will not start a new transaction in cycle 8, since it will
complicate that master’s grant logic.
Figure 162. Arbitration When GrantRemove Bit in EXP_MST_CONTROL is Clear
B4461-01
EX_CLK
- 0 -
- 1 -
- 2 -
- 3 -
- 4 -
- 5 -
- 6 -
- 7 -
- 8 -
- 9 -
EX_CS_N/
EX_IXPCS_N
EXPANSION BUS
OUTPUTS
EX_REQ0_IXPGNT_N
EX_GNT0_ IXPREQ_N
EX_REQ_N[1]
EX_GNT_N[1]
STATE
- 10 -
ARBITRATE
GNT MST0
ARBITRATE
GNT MST1
Arbiter monitors
EX_CS_N/
EX_IXPCS_ N
before asserting
EX_GNT[1]
