Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Intel XScale
®
Processor
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
198
Order Number: 306262-004US
Assume that we have the following data:
• N1
B
.............. Number of cycles to execute the if_stmt assuming the use of branch
instructions
• N2
B
...........Number of cycles to execute the else_stmt assuming the use of branch
instructions
• P1................................... Percentage of times the if_stmt is likely to be executed
• P2.......... Percentage of times we are likely to incur a branch misprediction penalty
• N1
C
... Number of cycles to execute the if-else portion using conditional instructions
assuming the if-condition to be true
• N2
C
... Number of cycles to execute the if-else portion using conditional instructions
assuming the if-condition to be false
Once we have the above data, use conditional instructions when:
The following example illustrates a situation in which we are better off using branches
over conditional instructions. Consider the code sample shown below:
In the above code sample, the cmp instruction takes 1 cycle to execute, the if-part
takes 7 cycles to execute and the else-part takes 6 cycles to execute. If we were to
change the code above so as to eliminate the branch instructions by making use of
conditional instructions, the if-else part would always take 10 cycles to complete.
If we make the assumptions that both paths are equally likely to be taken and that
branches are mis-predicted 50% of the time, the costs of using conditional execution
Vs using branches can be computed as follows:
Cost of using conditional instructions:
if (cond)
if_stmt
else
else_stmt
N
1
C
P
1
100
---------
×
⎝
⎠
⎛
⎞
N
2
C
100
P
1
–
100
----------------------
×
⎝
⎠
⎛
⎞
N
1
B
P
1
100
---------
×
⎝
⎠
⎛
⎞
N
2
B
100
P
1
–
100
----------------------
×
⎝
⎠
⎛
⎞
P
2
100
---------
4
×
⎝
⎠
⎛
⎞
+
+
≤
+
cmp r0, #0
bne L1
add r0, r0, #1
add r1, r1, #1
add r2, r2, #1
add r3, r3, #1
add r4, r4, #1
b L2
L1:
sub r0, r0, #1
sub r1, r1, #1
sub r2, r2, #1
sub r3, r3, #1
sub r4, r4, #1
L2:
