Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262--, Revision: 004US
327
USB 1.1 Device Controller—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network
Processors
8.5.17.7
Bit 6 Reserved
Bit 6 is reserved for future use.
8.5.17.8
Transmit Short Packet (TSP)
Software uses the transmit short to indicate that the last byte of a data transfer has
been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized
packet is ready to transmit. Software must not set this bit if a packet of 8 bytes is to be
transmitted.
When the data packet is successfully transmitted, the UDC clears this bit.
Register Name:
UDCCS15
Hex Offset Address:
0x C800B04C
Reset Hex Value:
0x00000001
Register
Description:
Universal Serial Bus Device Controller Endpoint 15 Control and Status Register
Access: Read/Write
Bits
31
8
7
6
5
4
3
2
1
0
(Reserved)
TS
P
(Rsvd
)
FS
T
SS
T
TUR
FT
F
TPC
TF
S
X
0
0
0
0
0
0
0
1
Resets (Above)
Register
UDCCS15
Bits
Name
Description
31:8
Reserved for future use.
7
TSP
Transmit short packet (read/write 1 to set).
1 = Short packet ready for transmission.
6
(Reserved). Always reads 0.
5
FST
Force STALL (read/write).
1 = Issue STALL handshakes to IN tokens.
4
SST
Sent STALL (read/write 1 to clear).
1 = STALL handshake was sent.
3
TUR
Transmit FIFO underrun (read/write 1 to clear).
1 = Transmit FIFO experienced an underrun.
2
FTF
Flush Tx FIFO (always read 0/ write a 1 to set).
1 = Flush Contents of TX FIFO.
1
TPC
Transmit packet complete (read/write 1 to clear).
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
0
TFS
Transmit FIFO service (read-only).
0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for 1 complete data packet.