Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors—Memory Controller
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer’s Manual
August 2006
612
Order Number: 306262-004US
11.2.2.12 DDRI SDRAM Refresh Cycle
Since the DDRI SDRAM is a dynamic memory, the MCU issues a refresh cycle
periodically. The interval of these refresh cycles is programmable in the RFR register.
The DDRI SDRAM device generates the refresh address internally. The MCU initiates
two sequential refresh cycles (one per bank) after the MCUs refresh timer expires and
any current transaction is complete. To preserve the correct refresh period, the refresh
timer continues counting after it expires to prevent a gradual skewing of the refresh
interval. The waveform in
illustrates the case where the refresh timer
expires while the memory bus is not busy.
Figure 116. DDRI SDRAM Pipelined Writes
B0408-02
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
CK_N
CK
Write
Write
Write
Write
Write
Address
Bank
Col b
Bank
Col x
Bank
Col n
Do
b
Do
b'
Do
x
Do
x'
Do
n'
Do
a
Do
a'
Do
n
Bank
Col a
Bank
Col g
ADDRESS Max
DQS
DI vs Do
DM
= Don't Care
Notes:
- DI b, etc. = Data In for column b, etc.
- DI b', etc. = the next Data in following DI b, etc. according to the programmed burst order
- Burst Length = 4 is shown.
- Write command may be to any bank and may be in the same or different devices.
