7.10.7.4
Logic diagram
GUID-0A1565A4-74E1-4171-968B-50529AABF192 v2
IEC10000214-1-en.vsd
StartCurr
X
a
b
a>b
Voltage
control or
restraint
feature
Inverse
DEF time
selected
Inverse
time
selected
OR
STOC
TROC
MinPh-PhVoltage
MaxPhCurr
IEC10000214 V1 EN-US
Figure 124:
Simplified internal logic diagram for overcurrent function
Operation_UV=On
StartVolt
AND
a
b
b>a
MinPh-phVoltage
BLKUV
IEC10000213-1-en.vsd
DEF time
selected
STUV
TRUV
IEC10000213 V1 EN-US
Figure 125:
Simplified internal logic diagram for undervoltage function
7.10.7.5
Undervoltage protection
GUID-96171DC7-9F8E-47B4-BE0D-E1B9EE214612 v5
The undervoltage step simply compares the magnitude of the lowest measured
phase-phase voltage quantity with the set start level. The undervoltage step starts if
the magnitude of the measured voltage quantity is lower than the set level.
The start signal starts a definite time delay. If the value of the start signal is logical
TRUE for longer than the set time delay, the undervoltage step sets its trip signal to
logical TRUE.
Section 7
1MRK 506 382-UEN A
Current protection
256
Line distance protection REL650 2.2 IEC
Technical manual
Summary of Contents for RELION 650 SERIES
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