Inter-Integrated Circuit Controller
7-72
Transmit Data Ready (XRDY)
Transmit mode only.
XRDY (bit 4) is set to 1 when I
2
C peripheral is a master or slave transmitter,
the local host is able to write a new data into the I2C_DATA register, and the
transmitter still requires a new data. A master transmitter requests new data
if DCOUNT
≠
0, and a slave transmitter requests new data if a read request
from external master.
Note:
The transmitter requests 2 bytes to be written even if only a single byte is
needed. In this case, the other byte must be filled with a dummy 0x00 value
that is not transmitted over the I
2
C line.
XRDY is automatically cleared to 0 by the core when I2C_DATA is written and
the transmit FIFO buffer is full. The local host can also poll this bit to write newly
transmitted data into I2C_DATA register.
-
0: Transmit buffer full (or receiver mode)
-
1: Transmit data ready (for write) and byte is needed.
Value after reset is low.
Receive Data Ready (RRDY)
RRDY (bit 3) is set to 1 when the local host is able to read new data from the
I2C_DATA register. RRDY is automatically cleared to 0 by the core when the
I2C_DATA is read and the receive FIFO buffer is empty. The local host can also
poll this bit to read the received data in the I2C_DATA register.
Interrupt mode, the local host needs to poll this bit after each read to I2C_DATA
to ensure that there is no other data on the FIFO waiting to be read. Indeed,
the RRDY must be cleared to 0 to receive a new RRDY interrupt.
-
0: Receive buffer empty
-
1: Receive data ready (for read)
Value after reset is low.
