UART/IrDA Functional Description
12-96
12.9.8 Break and Time-Out Conditions
-
time-out counter
An RX idle condition is detected when the receiver line, RX, has been high
for a time equivalent to 4 X programmed word 12 bits. The receiv-
er line is sampled midway through each bit.
For sleep mode, the counter is reset when there is activity on the RX line.
For the time-out interrupt, the counter only counts when there is data in the
RX FIFO and the count is reset when there is activity on the RX line or
when the RHR is read.
-
Break condition
When a break condition occurs, the TX line is pulled low. A break condition
is activated by setting LCR[6]. The break condition is not aligned on word
stream; that is, a break condition can occur in the middle of a character.
The only way to send a break condition on a full character, is:
J
Reset transmit FIFO (if enabled).
J
Wait for transmit shift register becomes empty (LSR[6] = 1).
J
Take a guard time according to stop bit definition.
J
Set LCR[6] to 1.
The break condition is asserted as long as LCR[6] is set to 1.
12.9.9 Programmable Baud Rate Generator
The programmable baud generator takes any clock input and divides it by a
divisor between 1 and (2
16-1)
.
The CLKSEL register bit MCR[7] can be used
to select the 1X or 1X/4 clock for the internal baud rate generator. The output
frequency of the baud rate generator is 16x the baud rate.
You must write to the DLL register (least significant bytes) and DLH register
(most significant bytes) of the baud rate divisor to program the baud rate.
Writing to these registers may result in wait states being inserted during the
write access while the baud rate generator is loaded with the new value. If
both registers are 0, the module is effectively disabled, and no baud clock is
generated.
Note:
The programmable baud rate generator selects both the transmit and
receive clock rates.
