UART/IrDA Functional Description
12-91
UART Devices
12.9.3.3
Wake-Up Interrupt
Wake-up interrupt is a uniquely designed interrupt, enabled when SCR[4] is
set to 1. The IIR register is not modified when it occurs; SSR[1] must be
checked to detect a wake-up event. When a wake-up interrupt occurs, the only
way to clear it is to reset SCR[4] to 0.
12.9.4 FIFO Interrupt Mode
In FIFO interrupt mode (FCR[0] = 1), relevant interrupts enabled via IER), the
processor is informed of the status of the receiver and transmitter by an inter-
rupt signal, IRQ. These interrupts are raised when receive/transmit FIFO
threshold (respectively TLR[7:4] and TLR[3:0] or FCR[7:6] and FCR[5:4]) are
reached; they ask the host (MPU or DSP) to transfer data to destination (from
UART module in receive mode and from any source to UART FIFO in transmit
mode).
When UART flow control is enabled along with interrupt capabilities, you must
ensure that the UART flow control FIFO threshold (TCR[3:0]) is greater than
or equal to the receive FIFO threshold.
Figure 12–18 and Figure 12–19 show the receive and transmit IT operations,
respectively.
Figure 12–18. Receive FIFO IT Request Generation
Programmable FIFO threshold
Receive FIFO level
Zero byte
time
Interrupt request
time
Interrupt request active low
Programmable flow control threshold
Host acknowledged IT request
and transferred enough bytes to
recover FIFO level below
threshold
In receive, no interrupt is generated until receive FIFO reaches its threshold.
Once low, the interrupt can only be deasserted when the host (MPU or DSP)
has handled enough bytes to make the FIFO level below threshold. Notice that
the flow control threshold is set at a higher value than the FIFO threshold.
